Cypress Semiconductor NoBL CY7C1471V25 Manual Download Page 25

Page: 25 / 32

CY7C1471V25
CY7C1473V25
CY7C1475V25

Document #: 38-05287 Rev. *I

Page 25 of 32

Figure 2

shows NOP, STALL and DESELECT Cycles waveform.

[19, 20, 22]

Figure 2. NOP, STALL and DESELECT Cycles

Switching Waveforms

(continued)

READ

Q(A3)

D(A4)

CLK

CEN

[A:D]

ADV/LD

ADDRESS

COMMAND

WRITE

D(A4)

STALL

WRITE

D(A1)

READ

Q(A2)

STALL

NOP

READ

Q(A5)

DESELECT

CONTINUE

DESELECT

DON’T CARE

UNDEFINED

tCHZ

Q(A2)

D(A1)

Q(A3)

tDOH

Q(A5)

Note

22. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle.

[+] Feedback

Summary of Contents for NoBL CY7C1471V25

Page 1: ...are 2 5V 2M x 36 4M x 18 1M x 72 synchronous flow through burst SRAMs designed specifically to support unlimited true back to back read or write operations without the insertion of wait states The CY7C1471V25 CY7C1473V25 and CY7C1475V25 are equipped with the advanced No Bus Latency NoBL logic required to enable consecutive read or write operations with data transferred on every clock cycle This fe...

Page 2: ...IC A0 A1 D1 D0 Q1 Q0 A0 A1 ADV LD CE ADV LD C CLK CEN WRITE DRIVERS D A T A S T E E R I N G S E N S E A M P S WRITE ADDRESS REGISTER A0 A1 A O U T P U T B U F F E R S E ZZ SLEEP CONTROL C MODE BWA BWB WE CE1 CE2 CE3 OE READ LOGIC DQs DQPA DQPB MEMORY ARRAY E INPUT REGISTER ADDRESS REGISTER WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC BURST LOGIC A0 A1 D1 D0 Q1 Q0 A0 A1 ADV LD CE ADV LD C CLK CE...

Page 3: ...A T A S T E E R I N G O U T P U T B U F F E R S MEMORY ARRAY E E INPUT REGISTER 0 ADDRESS REGISTER 0 WRITE ADDRESS REGISTER 1 BURST LOGIC A0 A1 D1 D0 Q1 Q0 A0 A1 C ADV LD ADV LD E INPUT REGISTER 1 S E N S E A M P S O U T P U T R E G I S T E R S E CLK CEN WRITE DRIVERS BW a BW b WE ZZ BW c BW d BW e BW f BW g BW h Sleep Control WRITE ADDRESS REGISTER 2 WRITE REGISTRY AND DATA COHERENCY CONTROL LOGI...

Page 4: ...QC VSS VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSS DQD DQD DQD DQD VSS VDDQ DQD DQD DQPD A A CE 1 CE 2 BW D BW C BW B BW A CE 3 V DD V SS CLK WE CEN OE A A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 ...

Page 5: ...NC DQB DQB VSS VDDQ DQB DQB NC VDD NC VSS DQB DQB VDDQ VSS DQB DQB DQPB NC VSS VDDQ NC NC NC A A CE 1 CE 2 NC NC BW B BW A CE 3 V DD V SS CLK WE CEN OE A A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 ...

Page 6: ...QB NC DQB NC DQA DQA VDD VDDQ VDD VDDQ DQB VDD NC VDD DQA VDD VDDQ DQA VDDQ VDD VDD VDDQ VDD VDDQ DQA VDDQ A A VSS A A A DQB DQB DQB ZZ DQA DQA DQPA DQA A VDDQ A A0 A VSS NC CY7C1473V25 4M x 18 2 3 4 5 6 7 1 A B C D E F G H J K L M N P R TDO NC 576M NC 1G NC NC DQPB NC DQB CE1 NC CE3 BWB CEN A CE2 NC DQB DQB MODE NC DQB DQB NC NC NC A VDDQ NC BWA CLK WE VSS VSS VSS VSS VDDQ VSS VDD VSS VSS VSS VSS...

Page 7: ...Qf NC DQa DQa DQa DQa DQPe DQe DQe DQe DQe A A A A NC NC NC 144M A A NC 288M A A A A A A A1 A0 A A A A A A NC 576M NC NC NC NC NC BWSb BWSf BWSe BWSa BWSc BWSg BWSd BWSh TMS TDI TDO TCK NC NC MODE NC CEN VSS NC CLK NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS NC 1G VDD NC OE CE3 CE1 CE2 ADV LD WE VSS VSS VSS VSS VSS VSS VSS ZZ VSS VSS VSS VSS NC VDDQ V...

Page 8: ...uring the data portion of a write sequence during the first clock when emerging from a deselected state when the device has been deselected CEN Input Synchronous Clock Enable Input Active LOW When asserted LOW the clock signal is recognized by the SRAM When deasserted HIGH the clock signal is masked Because deasserting CEN does not deselect the device CEN can be used to extend the previous cycle w...

Page 9: ...address into the SRAM as described in the Single Read Access section The sequence of the burst counter is determined by the MODE input signal A LOW input on MODE selects a linear burst mode a HIGH selects an inter leaved burst sequence Both burst counters use A0 and A1 in the burst sequence and wraps around when incremented sufficiently A HIGH input on ADV LD increments the internal burst counter ...

Page 10: ...of data Sleep Mode The ZZ input pin is an asynchronous input Asserting ZZ places the SRAM in a power conservation sleep mode Two clock cycles are required to enter into or exit from this sleep mode While in this mode data integrity is guaranteed Accesses pending when entering the sleep mode are not considered valid nor is the completion of the operation guaranteed The device must be deselected bef...

Page 11: ...ne L H L L L L H X L L H Tri State Write Abort Continue Burst Next X X X L H X H X L L H Tri State Ignore Clock Edge Stall Current X X X L X X X X H L H Sleep Mode None X X X H X X X X X X Tri State Notes 2 X Don t Care H Logic HIGH L Logic LOW BWX L signifies at least one Byte Write Select is active BWX Valid signifies that the desired Byte Write Selects are asserted see Truth Table for Read Writ...

Page 12: ...L L L Truth Table for Read Write The read write truth table for CY7C1473V25 follows 2 3 9 Function WE BWb BWa Read H X X Write No Bytes Written L H H Write Byte a DQa and DQPa L H L Write Byte b DQb and DQPb L L H Write Both Bytes L L L Truth Table for Read Write The read write truth table for CY7C1475V25 follows 2 3 9 Function WE BWx Read H X Write No Bytes Written L H Write Byte X DQx and DQPx L...

Page 13: ...ds to the TAP controller and is sampled on the rising edge of TCK It is allowable to leave this ball unconnected if the TAP is not used The ball is pulled up internally resulting in a logic HIGH level Test Data In TDI The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers The register between TDI and TDO is chosen by the inst...

Page 14: ...and must not be used The other five instructions are described in this section in detail The TAP controller used in this SRAM is not fully compliant to the 1149 1 convention because some of the mandatory 1149 1 instructions are not fully implemented The TAP controller cannot be used to load address data or control signals into the SRAM and cannot preload the IO buffers The SRAM does not implement ...

Page 15: ...is captured it is possible to shift out the data by putting the TAP into the Shift DR state This places the boundary scan register between the TDI and TDO balls Note that since the PRELOAD part of the command is not implemented putting the TAP to the Update DR state while performing a SAMPLE PRELOAD instruction has the same effect as the Pause DR command BYPASS When the BYPASS instruction is loade...

Page 16: ...ock LOW to TDO Valid 10 ns tTDOX TCK Clock LOW to TDO Invalid 0 ns Setup Times tTMSS TMS Setup to TCK Clock Rise 5 ns tTDIS TDI Setup to TCK Clock Rise 5 ns tCS Capture Setup to TCK Rise 5 ns Hold Times tTMSH TMS Hold after TCK Clock Rise 5 ns tTDIH TDI Hold after Clock Rise 5 ns tCH Capture Hold after Clock Rise 5 ns Notes 10 tCS and tCH refer to the setup and hold time requirements of latching d...

Page 17: ... 2 0 V VOH2 Output HIGH Voltage IOH 100 µA VDDQ 2 5V 2 1 V VDDQ 1 8V 1 6 V VOL1 Output LOW Voltage IOL 1 0 mA VDDQ 2 5V 0 4 V VOL2 Output LOW Voltage IOL 100 µA VDDQ 2 5V 0 2 V VDDQ 1 8V 0 2 V VIH Input HIGH Voltage VDDQ 2 5V 1 7 VDD 0 3 V VDDQ 1 8V 1 26 VDD 0 3 V VIL Input LOW Voltage VDDQ 2 5V 0 3 0 7 V VDDQ 1 8V 0 3 0 36 V IX Input Load Current GND VIN VDDQ 5 5 µA Identification Register Defini...

Page 18: ...er between TDI and TDO This operation does not affect SRAM operations SAMPLE Z 010 Captures IO ring contents Places the boundary scan register between TDI and TDO Forces all SRAM output drivers to a High Z state RESERVED 011 Do Not Use This instruction is reserved for future use SAMPLE PRELOAD 100 Captures IO ring contents Places the boundary scan register between TDI and TDO Does not affect SRAM ...

Page 19: ... 31 P10 51 G10 71 B2 12 L1 32 R9 52 F10 13 J2 33 R10 53 E10 14 M1 34 R11 54 A9 15 N1 35 N11 55 B9 16 K2 36 M11 56 A10 17 L2 37 L11 57 B10 18 M2 38 M10 58 A8 19 R1 39 L10 59 B8 20 R2 40 K11 60 A7 Boundary Scan Exit Order 4M x 18 Bit 165 Ball ID Bit 165 Ball ID Bit 165 Ball ID Bit 165 Ball ID 1 D2 14 R4 27 L10 40 B10 2 E2 15 P6 28 K10 41 A8 3 F2 16 R6 29 J10 42 B8 4 G2 17 R8 30 H11 43 A7 5 J1 18 P3 ...

Page 20: ...1 A9 8 D2 36 W2 64 N11 92 U8 9 E1 37 T6 65 N10 93 A6 10 E2 38 V3 66 M11 94 D6 11 F1 39 V4 67 M10 95 K6 12 F2 40 U4 68 L11 96 B6 13 G1 41 W5 69 L10 97 K3 14 G2 42 V6 70 P6 98 A8 15 H1 43 W6 71 J11 99 B4 16 H2 44 V5 72 J10 100 B3 17 J1 45 U5 73 H11 101 C3 18 J2 46 U6 74 H10 102 C4 19 L1 47 W7 75 G11 103 C8 20 L2 48 V7 76 G10 104 C9 21 M1 49 U7 77 F11 105 B9 22 M2 50 V8 78 F10 106 B8 23 N1 51 V9 79 E...

Page 21: ... IO 1 7 VDD 0 3V V For 1 8V IO 1 26 VDD 0 3V V VIL Input LOW Voltage 13 For 2 5V IO 0 3 0 7 V For 1 8V IO 0 3 0 36 V IX Input Leakage Current except ZZ and MODE GND VI VDDQ 5 5 µA Input Current of MODE Input VSS 30 µA Input VDD 5 µA Input Current of ZZ Input VSS 5 µA Input VDD 30 µA IOZ Output Leakage Current GND VI VDDQ Output Disabled 5 5 µA IDD VDD Operating Supply Current VDD Max IOUT 0 mA f f...

Page 22: ...esign or process change that may affect these parameters Parameter Description Test Conditions 100 TQFP Package 165 FBGA Package 209 FBGA Package Unit ΘJA Thermal Resistance Junction to Ambient Test conditions follow standard test methods and procedures for measuring thermal impedance according to EIA JESD51 24 63 16 3 15 2 C W ΘJC Thermal Resistance Junction to Case 2 28 2 1 1 7 C W AC Test Loads...

Page 23: ...S Data Input Setup Before CLK Rise 1 5 1 5 ns tCES Chip Enable Setup Before CLK Rise 1 5 1 5 ns Hold Times tAH Address Hold After CLK Rise 0 5 0 5 ns tALH ADV LD Hold After CLK Rise 0 5 0 5 ns tWEH WE BWX Hold After CLK Rise 0 5 0 5 ns tCENH CEN Hold After CLK Rise 0 5 0 5 ns tDH Data Input Hold After CLK Rise 0 5 0 5 ns tCEH Chip Enable Hold After CLK Rise 0 5 0 5 ns Notes 15 This part has a volt...

Page 24: ...OMMAND tCLZ D A1 D A2 Q A4 Q A3 D A2 1 tDOH tCHZ tCDV WRITE D A2 BURST WRITE D A2 1 READ Q A3 READ Q A4 BURST READ Q A4 1 WRITE D A5 READ Q A6 WRITE D A7 DESELECT OE tOEV tOELZ tOEHZ DON T CARE UNDEFINED D A5 tDOH Q A4 1 D A7 Q A6 Notes 19 For this waveform ZZ is tied LOW 20 When CE is LOW CE1 is LOW CE2 is HIGH and CE3 is LOW When CE is HIGH CE1 is HIGH CE2 is LOW or CE3 is HIGH 21 Order of the B...

Page 25: ...s continued READ Q A3 4 5 6 7 8 9 10 A3 A4 A5 D A4 1 2 3 CLK CE WE CEN BW A D ADV LD ADDRESS DQ COMMAND WRITE D A4 STALL WRITE D A1 READ Q A2 STALL NOP READ Q A5 DESELECT CONTINUE DESELECT DON T CARE UNDEFINED tCHZ A1 A2 Q A2 D A1 Q A3 tDOH Q A5 Note 22 The IGNORE CLOCK EDGE or STALL cycle Clock 3 illustrates CEN being used to create a pause A write is not performed during this cycle Feedback ...

Page 26: ...Switching Waveforms continued t ZZ I SUPPLY CLK ZZ tZZREC ALL INPUTS except ZZ DON T CARE I DDZZ tZZI tRZZI Outputs Q High Z DESELECT or READ Only Notes 23 Device must be deselected when entering ZZ mode See Truth Table on page 11 for all possible signal conditions to deselect the device 24 DQs are in high Z when exiting ZZ sleep mode Feedback ...

Page 27: ...CY7C1471V25 133BZXI 51 85165 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Pb Free CY7C1473V25 133BZXI CY7C1475V25 133BGI 51 85167 209 Ball Fine Pitch Ball Grid Array 14 22 1 76 mm CY7C1475V25 133BGXI 209 Ball Fine Pitch Ball Grid Array 14 22 1 76 mm Pb Free 100 CY7C1471V25 100AXC 51 85050 100 Pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Pb Free Commercial CY7C1473V25 100AXC CY7C1471V25 100BZC ...

Page 28: ...SION END FLASH SHALL NOT EXCEED 0 0098 in 0 25 mm PER SIDE 3 DIMENSIONS IN MILLIMETERS BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 0 30 0 08 0 65 20 00 0 10 22 00 0 20 1 40 0 05 12 1 1 60 MAX 0 05 MIN 0 60 0 15 0 MIN 0 25 0 7 8X STAND OFF R 0 08 MIN TYP 0 20 MAX 0 15 MAX 0 20 MAX R 0 08 MIN 0 20 MAX 14 00 0 10 16 00 0 20 0 10 SEE DETAIL A DETAIL A 1 100 30 0 5 1 3 51 8...

Page 29: ... A 1 PIN 1 CORNER 17 00 0 10 15 00 0 10 7 00 1 00 Ø0 45 0 05 165X Ø0 25 M C A B Ø0 05 M C B A 0 15 4X 0 35 1 40 MAX SEATING PLANE 0 53 0 05 0 25 C 0 15 C PIN 1 CORNER TOP VIEW BOTTOM VIEW 2 3 4 5 6 7 8 9 10 10 00 14 00 B C D E F G H J K L M N 11 11 10 9 8 6 7 5 4 3 2 1 P R P R K M N L J H G F E D C B A C 1 00 5 00 0 36 0 05 0 10 51 85165 A Feedback ...

Page 30: ...ress written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifie...

Page 31: ...21 E 299511 See ECN SYT Removed 117 MHz Speed Bin Changed ΘJA from 16 8 to 24 63 C W and ΘJC from 3 3 to 2 28 C W for 100 TQFP Package on Page 22 Added Pb free information for 100 Pin TQFP 165 FBGA and 209 BGA Packages Added comment of Pb free BG packages availability below the Ordering Information F 323039 See ECN PCI Address expansion pins balls in the pinouts for all packages are modified as pe...

Page 32: ...Relative to GND Changed tTH tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC Switching Characteristics table Updated the Ordering Information table I 1274732 See ECN VKN AESA Corrected typo in the NOP STALL and DESELECT Cycles waveform Document Title CY7C1471V25 CY7C1473V25 CY7C1475V25 72 Mbit 2M x 36 4M x 18 1M x 72 Flow Through SRAM with NoBL Architecture Document Number 38 05287 R...

Search results

Summary of Contents for NoBL CY7C1471V25

Reviews:

Related manuals for NoBL CY7C1471V25

Brands by name

Popular brands

Cypress Semiconductor NoBL CY7C1471V25, Manual

Search results

Summary of Contents for NoBL CY7C1471V25

Reviews:

Related manuals for NoBL CY7C1471V25

Brands by name

Popular brands