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Revised April 1, 2009

Page 5 of 5

All products and company names mentioned in this document may be the trademarks of their respective holders.

CY7C68003

© Cypress Semiconductor Corporation, 2007-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. 

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress. 

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges. 

Use may be limited by and subject to the applicable Cypress software license agreement. 

The operation and configuration modes are described in

Operation Modes

 on page 4 and 

Configuration Mode

 on page 14

respectively. The ULPI Low power mode and Sleep mode are
described in the following sections:

ULPI Low Power Mode

In this mode, the link optionally places the TX2UL in low power
mode when the USB is suspended. TX2UL powers down all the
circuitry except for the interface pins and full speed receiver. To
enter low power mode, the link must set SuspendM in the
Function Control register to 0b. The TX2UL clock is stopped for
a minimum of five cycles after TX2UL accepts the register write.
To exit the low power mode, the link signals TX2UL to exit the
mode by asynchronously asserting a signal, STP. The TX2UL
wakes up its internal circuitry and when it meets the ULPI timing
requirements it deasserts DIR. The SuspendM register is set to
1b.

Sleep Mode

Sleep mode is entered by asserting RESET_N during the Normal
Operation Mode. When RESET_N is driven low for tSTATE (see

Table 21

 on page 19 for tSTATE requirement) while CS_N is low,

TX2UL enters into Sleep Mode. VCC must remain supplied (ON)
during the sleep mode. This mode powers down all internal
circuitry except the RESET_N pin and the chip_config register.
The ULPI interface bus is tri-stated. 

During the Sleep Mode ensure that:

The ULPI interface IOs is either floating or driven high by the link

DP and DM are either floating or pull to 0V

Deassert RESET_N to exit the Sleep Mode.

VID and PID

The VID and PID are hard coded into Product ID and Vendor ID registers (read only) as shown in 

Table 6

.

Table 6.  Immediate Register Values for VID and PID

Field Name

Size (bit)

Address (6 bits)

Value

Rd

Wr

Set

Clr

Vendor ID (VID) Low

8

00h

-

-

-

B4h

Vendor ID (VID) High

8

01h

-

-

-

04h

Product ID (PID) Low

8

02h

-

-

-

03h

Product ID (PID) High

8

03h

-

-

-

68h

Summary of Contents for MoBL-USB CY7C68003

Page 1: ... Single Ended Device RESET Input UART Pass Through Mode ESD Compliance JESD22 A114D 8 kV Contact Human Body Model HBM for DP DM and VSS Pins IEC61000 4 2 8 kV Contact Discharge IEC61000 4 2 15 kV Air Discharge Support for Industrial Temperature Range 40 C to 85 C Low Power Consumption for Mobile Applications 5 uA Nominal Sleep Mode 30 mA Nominal Active HS Transfer Small Package for Mobile Applicat...

Page 2: ...h For more information about different modes of configu ration see Table 5 on page 4 DP and DM pins The DP and DM pins are the differential pins for the USB They must be connected to the corresponding DP and DM pins of the USB receptacle Chip Select CS_N This signal pin is available only in 24 pin QFN package The two major functions of CS_N are as follows Tri state the ULPI bus output pins Associa...

Page 3: ...O This is the 1 8V to 3 3V multi range supply to the I O ring It can range anywhere from 1 7V to 3 6V during actual operation VBATT This is the battery input supply that powers the 3 3V Regulator block It can range anywhere from 3 0 to 5 775V during actual operation Voltage Regulator The internal 3 3V regulator block regulates the VBATT supply to the internal 3 3V supply for the USBIO and XOSC blo...

Page 4: ...ired to de assert with tSTATE Change from Normal Operation Mode to Sleep Mode RESET_N is required to assert with tSTATE Figure 3 Mode Change State Diagram Normal Operation Mode Tri State ULPI Interface Output Mode available in 24 pin QFN package only Sleep Mode ULPI Low Power Mode Configuration Mode Carkit UART Pass Through Mode Table 4 TX2UL 20 Pin CPS Package Operation Modes RESET_N Mode 0 Low S...

Page 5: ...described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress product in a life support systems applicat...

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