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Cypress Semiconductor enCoRe V CY7C6431x, Specification Sheet, Page: 25 / 28

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Cypress Semiconductor enCoRe V CY7C6431x Specification Sheet Download Page 25

CY7C6431x

CY7C64345, CY7C6435x

Document Number: 001-12394 Rev *G

Page 25 of 28

Figure 11. 48-Pin (7 x 7 x 0.9 mm) QFN

Package Handling

Some IC packages require baking before they are soldered onto a PCB to remove moisture that may have been absorbed after leaving
the factory. A label on the package has details about the actual bake temperature and the minimum bake time to remove this moisture.
The maximum bake time is the aggregate time that the parts exposed to the bake temperature. Exceeding this exposure may degrade
device reliability. 

Table 22.Package Handling

Parameter

Description

Minimum

Typical

Maximum

Unit

T

BAKETEMP

Bake Temperature

125

See package label

o

C

T

BAKETIME

Bake Time

See package label

72

hours

001-13191 *C

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Summary of Contents for enCoRe V CY7C6431x

Page 1: ...range is 19 to 50 kHz with a 32 kHz typical value Programmable Pin Configurations 25 mA sink current on all GPIO Pull Up High Z Open Drain CMOS drive modes on all GPIO Configurable inputs on all GPIO...

Page 2: ...wires SPI communication over three or four wires runs at speeds of 46 9 kHz to 3 MHz lower for a slower system clock In I2 C slave mode the hardware address recognition feature reduces the already lo...

Page 3: ...mlessly within the PSoC Designer interface and have been tested with a full range of debugging tools The choice is yours Assemblers The assemblers allow assembly code to be merged seamlessly with C co...

Page 4: ...each other with valuator functions In the chip level view you perform the selection configuration and routing so that you have complete control over the use of all on chip resources Generate Verify a...

Page 5: ...e h for example 14h or 3Ah Hexadecimal numbers may also be represented by a 0x prefix the C coding convention Binary numbers have an appended lowercase b for example 01010100b or 01000011b Numbers not...

Page 6: ...ng ISSP pins that are not High Z at power on reset POR Table 1 16 Pin Part Pinout QFN Pin No Type Name Description 1 I O P2 3 Digital I O Crystal Input Xin 2 IOHR P1 7 Digital I O SPI SS I2C SCL 3 IOH...

Page 7: ...Digital I O SPI CLK 8 IOHR P1 1 1 2 Digital I O ISSP CLK I2C SCL SPI MOSI 9 Power Vss Ground 10 I O D USB PHY 11 I O D USB PHY 12 Power Vdd Supply voltage 13 IOHR P1 0 1 2 Digital I O ISSP DATA I2C SD...

Page 8: ...Description 1 NC NC No connection 2 I O P2 7 Digital I O 3 I O P2 5 Digital I O Crystal Out Xout 4 I O P2 3 Digital I O Crystal In Xin 5 I O P2 1 Digital I O 6 I O P4 3 Digital I O 7 I O P4 1 Digital...

Page 9: ...I O P2 2 Digital I O 35 I O P2 4 Digital I O 36 I O P2 6 Digital I O 37 IOH P0 0 Digital I O 38 IOH P0 2 Digital I O 39 IOH P0 4 Digital I O 40 IOH P0 6 Digital I O 41 Power Vdd Supply voltage 42 NC...

Page 10: ...e has a total register address space of 512 bytes The register space is also referred to as IO space and is broken into two parts Bank 0 user space and Bank 1 configu ration space The XIO bit in the F...

Page 11: ...DR 5A RW 9A INT_CLR0 DA RW 1B PMA3_DR 5B RW 9B INT_CLR1 DB RW 1C PMA4_DR 5C RW 9C INT_CLR2 DC RW 1D PMA5_DR 5D RW 9D INT_CLR3 DD RW 1E PMA6_DR 5E RW 9E INT_MSK2 DE RW 1F PMA7_DR 5F RW 9F INT_MSK1 DF R...

Page 12: ..._CR0 54 94 D4 15 EP2_CR0 55 95 D5 16 EP3_CR0 56 96 D6 17 EP4_CR0 57 97 D7 18 EP5_CR0 58 98 D8 19 EP6_CRO 59 99 D9 1A EP7_CR0 5A 9A DA 1B EP8_CR0 5B 9B DB 1C 5C 9C IO_CFG DC RW 1D 5D 9D OUT_P1 DD RW 1E...

Page 13: ...ency Vdd Voltage 3 0V 3 MHz V a l i d O p e r a t i n g R e g i o n 5 5V 750 kHz 6 MHz 24 MHz IMO Frequency Vdd Voltage 3 MHz 3 0V SLIMO Mode 01 12 MHz SLIMO Mode 00 SLIMO Mode 10 Table 7 Units of Mea...

Page 14: ...ock DC Accuracy DNL 1 2 LSb For any configuration INL 2 2 LSb For any configuration Offset Error 0 15 90 mV Operating Current 275 350 A Data Clock 2 25 12 MHz Source is chip s internal main oscil lato...

Page 15: ...specific See Package Handling on page 25 The user must limit the power consumption to comply with this requirement Table 9 DC Chip Level Specifications Parameter Description Conditions Min Typ Max Un...

Page 16: ...IOH 10 A Vdd 3 0V maximum of 10 mA source current in all I Os Vdd 0 2 V VOH2 High Output Voltage Port 0 2 or 3 Pins IOH 1 mA Vdd 3 0 maximum of 20 mA source current in all I Os Vdd 0 9 V VOH3 High Ou...

Page 17: ...ysteresis Voltage 50 60 200 mV IIL Input Leakage Absolute Value 0 001 1 A CPIN Pin Capacitance Package and pin dependent Temp 25o C 0 5 1 7 5 pF Table 12 DC POR and LVD Specifications Symbol Descripti...

Page 18: ...ing Programming or Verify 8 1 5 mA VOLV Output Low Voltage During Programming or Verify Vss 0 75 V VOHV Output High Voltage During Programming or Verify Vdd 0 9 Vdd V FlashENPB Flash Write Endurance 9...

Page 19: ...jitter To next transition 3 5 3 5 ns Tudj2 Driver differential jitter To pair transition 4 0 4 0 ns Tfdeop Source jitter for differential transition To SE0 transition 2 5 ns Tfeopt Source SE0 interva...

Page 20: ...AC GPIO Specifications Symbol Description Conditions Min Typ Max Units FGPIO GPIO Operating Frequency Normal Strong Mode Ports 0 1 0 12 MHz TRise23 Rise Time Strong Mode Ports 2 3 Vdd 3 3 to 5 5V 10...

Page 21: ...ns TFSCLK Fall Time of SCLK 1 20 ns TSSCLK Data Setup Time to Falling Edge of SCLK 40 ns THSCLK Data Hold Time from Falling Edge of SCLK 40 ns FSCLK Frequency of SCLK 0 8 MHz TERASEB Flash Erase Time...

Page 22: ...Repeated START Condition 4 7 0 6 s THDDATI2C Data Hold Time 0 0 s TSUDATI2C Data Setup Time 250 100 15 ns TSUSTOI2C Setup Time for STOP Condition 4 0 0 6 s TBUFI2C Bus Free Time Between a STOP and ST...

Page 23: ...enCoRe V USB device along with the thermal impedances for each package Important Note Emulation tools may require a larger area on the target PCB than the chip s footprint For a detailed description...

Page 24: ...CY7C6431x CY7C64345 CY7C6435x Document Number 001 12394 Rev G Page 24 of 28 Figure 10 32 Pin 5 x 5 x 0 55 mm QFN 001 42168 C Feedback...

Page 25: ...ory A label on the package has details about the actual bake temperature and the minimum bake time to remove this moisture The maximum bake time is the aggregate time that the parts exposed to the bak...

Page 26: ...C64316 16LKXCT 16 Pin QFN Tape and Reel 3x3 mm 32K 2K 11 Hi end FS USB dongle RC host module CY7C64343 32LQXC 32 Pin QFN 3x3 mm 8K 1K 25 Full speed USB mouse CY7C64343 32LQXCT 32 Pin QFN 3X3 mm 8K 1K...

Page 27: ...ap tables Corrected a value in the DC Chip Level Specifications table C 1241024 TYJ ARI See ECN Corrected Idd values in Table 6 DC Chip Level Specifications D 1639963 AESA See ECN Post to www cypress...

Page 28: ...e used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except...

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