Cypress Semiconductor enCoRe V CY7C6431x, Specification Sheet, Page: 22 / 28

CY7C6431x
CY7C64345, CY7C6435x
Document Number: 001-12394 Rev *G Page 22 of 28
AC I
2
C Specifications
Table 21 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Figure 8. Definition of Timing for Fast/Standard Mode on the I
2
C Bus
Table 21. AC Characteristics of the I
2
C SDA and SCL Pins
Symbol Description
Standard Mode Fast Mode
Units
Min Max Min Max
F
SCLI2C
SCL Clock Frequency 0 100 0 400 kHz
T
HDSTAI2C
Hold Time (repeated) START Condition. After this period, the first
clock pulse is generated. 4.0 – 0.6 –
μ
s
T
LOWI2C
LOW Period of the SCL Clock 4.7 – 1.3 –
μ
s
T
HIGHI2C
HIGH Period of the SCL Clock 4.0 – 0.6 –
μ
s
T
SUSTAI2C
Setup Time for a Repeated START Condition 4.7 – 0.6 –
μ
s
T
HDDATI2C
Data Hold Time 0 – 0 –
μ
s
T
SUDATI2C
Data Setup Time 250 – 100
(15)
– ns
T
SUSTOI2C
Setup Time for STOP Condition 4.0 – 0.6 –
μ
s
T
BUFI2C
Bus Free Time Between a STOP and START Condition 4.7 – 1.3 –
μ
s
T
SPI2C
Pulse Width of spikes are suppressed by the input filter. – – 0 50 ns
Notes
15.
A Fast mode I2C bus device can be used in a standard mode I2C bus system, but the requirement t
SU;DAT
≥
250 ns must then be met. This is automatically the case if the device does not stretch the
LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line t
rmax
+ t
SU;DAT
= 1000 + 250 = 1250 ns (according to the
standard mode I2C bus specification) before the SCL line is released.
SDA
SCL
S Sr S P
T
BUFI2C
T
SPI2C
T
HDSTAI2C
T
SUSTOI2C
T
SUSTAI2C
T
LOWI2C
T
HIGHI2C
T
HDDATI2C
T
HDSTAI2C
T
SUDATI2C
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