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CY7C185

4

Switching Characteristics 

Over the Operating Range

[5]

7C185–15

7C185–20

7C185–25

7C185–35

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

READ CYCLE

t

RC

Read Cycle Time

15

20

25

35

ns

t

AA

Address to Data Valid

15

20

25

35

ns

t

OHA

Data Hold from
Address Change

3

5

5

5

ns

t

ACE1

CE

1

 LOW to Data Valid

15

20

25

35

ns

t

ACE2

CE

2

 HIGH to Data Valid

15

20

25

35

ns

t

DOE

OE LOW to Data Valid

8

9

12

15

ns

t

LZOE

OE LOW to Low Z

3

3

3

3

ns

t

HZOE

OE HIGH to High Z

[6]

7

8

10

10

ns

t

LZCE1

CE

1

 LOW to Low Z

[7]

3

5

5

5

ns

t

LZCE2

CE

2

 HIGH to Low Z

3

3

3

3

ns

t

HZCE

CE

1

 HIGH to High Z

[6, 7]

CE

2

 LOW to High Z

7

8

10

10

ns

t

PU

CE

1

 LOW to Power-Up

CE

2

 to HIGH to Power-Up

0

0

0

0

ns

t

PD

CE

1

 HIGH to Power-Down

CE

LOW to Power-Down

15

20

20

20

ns

WRITE CYCLE

[8]

t

WC

Write Cycle Time

15

20

25

35

ns

t

SCE1

CE

1

 LOW to Write End

12

15

20

20

ns

t

SCE2

CE

2

 HIGH to Write End

12

15

20

20

ns

t

AW

Address Set-Up to
Write End

12

15

20

25

ns

t

HA

Address Hold from
Write End

0

0

0

0

ns

t

SA

Address Set-Up to
Write Start

0

0

0

0

ns

t

PWE

WE Pulse Width

12

15

15

20

ns

t

SD

Data Set-Up to Write End

8

10

10

12

ns

t

HD

Data Hold from Write End

0

0

0

0

ns

t

HZWE

WE LOW to High Z

[6]

7

7

7

8

ns

t

LZWE

WE HIGH to Low Z

3

5

5

5

ns

Notes:

5.

Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified 
I

OL

/I

OH

 and 30-pF load capacitance.

6.

t

HZOE, 

t

HZCE

, and t

HZWE

 are specified with C

L

 = 5 pF as in part (b) of AC Test Loads. Transition is measured 

±

500 mV from steady state voltage.

7.

At any given temperature and voltage condition, t

HZCE

 is less than t

LZCE1 

and t

LZCE2

 for any given device.

8.

The internal write time of the memory is defined by the overlap of CE

1

 LOW, CE

2

 HIGH, and WE LOW. All 3 signals must be active to initiate a write and either 

signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 

Summary of Contents for CY7C185

Page 1: ...mory location addressed by the address present on the address pins A0 through A12 Reading the device is accomplished by selecting the device and enabling the outputs CE1 and OE active LOW CE2 active HIGH while WE remains inactive or HIGH Under these conditions the contents of the location ad dressed by the information on address pins are present on the eight data input output pins The input output...

Page 2: ...Test Conditions Min Max Min Max Unit VOH Output HIGH Voltage VCC Min IOH 4 0 mA 2 4 2 4 V VOL Output LOW Voltage VCC Min IOL 8 0 mA 0 4 0 4 V VIH Input HIGH Voltage 2 2 VCC 0 3V 2 2 VCC 0 3V V VIL Input LOW Voltage 2 0 5 0 8 0 5 0 8 V IIX Input Load Current GND VI VCC 5 5 5 5 µA IOZ Output Leakage Current GND VI VCC Output Disabled 5 5 5 5 µA IOS Output Short Circuit Current 3 VCC Max VOUT GND 300...

Page 3: ...ating Supply Current VCC Max IOUT 0 mA 100 100 mA ISB1 Automatic Power Down Current Max VCC CE1 VIH or CE2 VIL Min Duty Cycle 100 20 20 mA ISB2 Automatic Power Down Current Max VCC CE1 VCC 0 3V or CE2 0 3V VIN VCC 0 3V or VIN 0 3V 15 15 mA Capacitance 4 Parameter Description Test Conditions Max Unit CIN Input Capacitance TA 25 C f 1 MHz VCC 5 0V 7 pF COUT Output Capacitance 7 pF Note 4 Tested init...

Page 4: ...Address Set Up to Write End 12 15 20 25 ns tHA Address Hold from Write End 0 0 0 0 ns tSA Address Set Up to Write Start 0 0 0 0 ns tPWE WE Pulse Width 12 15 15 20 ns tSD Data Set Up to Write End 8 10 10 12 ns tHD Data Hold from Write End 0 0 0 0 ns tHZWE WE LOW to High Z 6 7 7 7 8 ns tLZWE WE HIGH to Low Z 3 5 5 5 ns Notes 5 Test conditions assume signal transition time of 5 ns or less timing refe...

Page 5: ...put set up and hold timing should be referenced to the rising edge of the signal that terminates the write 13 During this period the I Os are in the output state and input signals should not be applied ADDRESS DATA OUT PREVIOUS DATA VALID DATA VALID tRC tAA tOHA C185 6 Read Cycle No 1 9 10 50 50 DATA VALID tRC tACE tDOE tLZOE tLZCE tPU HIGH IMPEDANCE IMPEDANCE ICC ISB tHZOE tHZCE tPD OE HIGH DATA ...

Page 6: ...with WE HIGH the output remains in a high impedance state Switching Waveforms continued tWC tAW tSA tHA tHD tSD tSCE1 WE DATA I O ADDRESS CE1 C185 9 DATA IN VALID tSCE2 CE2 Write Cycle No 2 CE Controlled 12 13 14 tHD tSD tLZWE tSA tHA tAW tWC tHZWE C185 10 DATA IN VALID tSCE1 tSCE2 CE1 CE2 ADDRESS DATA I O WE Write Cycle No 3 WE Controlled OE LOW 12 13 14 15 NOTE 13 ...

Page 7: ...GE 0 0 0 8 1 4 1 3 1 2 1 1 1 0 0 9 4 0 4 5 5 0 5 5 6 0 NORMALIZED t AA SUPPLY VOLTAGE V NORMALIZED ACCESS TIME vs SUPPLY VOLTAGE 120 140 100 60 40 20 0 0 1 0 2 0 3 0 4 0 OUTPUT SINK CURRENT mA 0 80 OUTPUT VOLTAGE V OUTPUT SINK CURRENT vs OUTPUT VOLTAGE NORMALIZED I I CC SB I CC VCC 5 0V VCC 5 0V TA 25 C VCC 5 0V TA 25 C I SB TA 25 C 0 6 0 8 0 3 0 2 5 2 0 1 5 1 0 0 5 0 0 1 0 2 0 3 0 4 0 NORMALIZED ...

Page 8: ... 28 Lead 300 Mil Molded DIP Commercial CY7C185 15SC S21 28 Lead Molded SOIC CY7C185 15VC V21 28 Lead Molded SOJ CY7C185 15VI V21 28 Lead Molded SOJ Industrial 20 CY7C185 20PC P21 28 Lead 300 Mil Molded DIP Commercial CY7C185 20SC S21 28 Lead Molded SOIC CY7C185 20VC V21 28 Lead Molded SOJ CY7C185 20VI V21 28 Lead Molded SOJ Industrial 25 CY7C185 25PC P21 28 Lead 300 Mil Molded DIP Commercial CY7C1...

Page 9: ...CY7C185 9 Package Diagrams 51 85014 B 28 Lead 300 Mil Molded DIP P21 28 Lead 300 Mil Molded SOIC S21 51 85026 A ...

Page 10: ... patent or other rights Cypress Semiconductor does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress Semiconductor products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemn...

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