Cypress Semiconductor CY7C1510KV18 Specification Sheet Download Page 21

Page: 21 / 30

CY7C1510KV18, CY7C1525KV18
CY7C1512KV18, CY7C1514KV18

Document Number: 001-00436 Rev. *E

Page 21 of 30

[19]

Operating Supply

= Max,

OUT

= 0 mA,

f = f

MAX

= 1/t

CYC

200 MHz (x8)

540

(x9)

540

(x18)

550

(x36)

660

167 MHz (x8)

480

(x9)

480

(x18)

490

(x36)

580

SB1

Automatic Power Down

Current

Max V

Both Ports Deselected,

≥

or V

≤

f = f

MAX

= 1/t

CYC

Inputs Static

333 MHz (x8)

290

(x9)

290

(x18)

290

(x36)

290

300 MHz (x8)

280

(x9)

280

(x18)

280

(x36)

280

250 MHz (x8)

270

(x9)

270

(x18)

270

(x36)

270

200 MHz (x8)

250

(x9)

250

(x18)

250

(x36)

250

167 MHz (x8)

250

(x9)

250

(x18)

250

(x36)

250

AC Electrical Characteristics

Over the Operating Range

[11]

Parameter

Description

Test Conditions

Min

Typ

Max

Unit

Input HIGH Voltage

REF

+ 0.2

–

Input LOW Voltage

–

REF

– 0.2

Electrical Characteristics

(continued)

DC Electrical Characteristics

Over the Operating Range

[12]

Parameter

Description

Test Conditions

Min

Typ

Max

Unit

[+] Feedback

Summary of Contents for CY7C1510KV18

Page 1: ...ous Pipelined SRAMs equipped with QDR II architecture QDR II architecture consists of two separate ports the read port and the write port to access the memory array The read port has dedicated data ou...

Page 2: ...Read Data Reg RPS WPS Control Logic Address Register Reg Reg Reg 8 22 16 8 NWS 1 0 VREF Write Add Decode Write Reg 8 A 21 0 22 CQ CQ DOFF Q 7 0 8 8 Write Reg C C 4M x 8 Array 8 4M x 9 Array CLK A 21...

Page 3: ...a Reg RPS WPS Control Logic Address Register Reg Reg Reg 18 21 36 18 BWS 1 0 VREF Write Add Decode Write Reg 18 A 20 0 21 CQ CQ DOFF Q 17 0 18 18 Write Reg C C 2M x 18 Array 18 1M x 36 Array CLK A 19...

Page 4: ...Q6 D6 VDDQ VSS VSS VSS VDDQ NC NC Q0 M NC NC NC VSS VSS VSS VSS VSS NC NC D0 N NC D7 NC VSS A A A VSS NC NC NC P NC NC Q7 A A C A A NC NC NC R TDO TCK A A A C A A A TMS TDI CY7C1525KV18 8M x 9 1 2 3 4...

Page 5: ...A A NC D0 Q0 R TDO TCK A A A C A A A TMS TDI CY7C1514KV18 2M x 36 1 2 3 4 5 6 7 8 9 10 11 A CQ NC 288M A WPS BWS2 K BWS1 RPS A NC 144M CQ B Q27 Q18 D18 A BWS3 K BWS0 A D17 Q17 Q8 C D27 Q28 D19 VSS A A...

Page 6: ...8M x 8 2 arrays each of 4M x 8 for CY7C1510KV18 8M x 9 2 arrays each of 4M x 9 for CY7C1525KV18 4M x 18 2 arrays each of 2M x 18 for CY7C1512KV18 and 2M x 36 2 arrays each of 1M x 36 for CY7C1514KV18...

Page 7: ...s pin cannot be connected directly to GND or left unconnected DOFF Input PLL Turn Off Active LOW Connecting this pin to ground turns off the PLL inside the device The timing in the operation with the...

Page 8: ...at the rising edge of the positive input clock K On the same K clock rise the data presented to D 17 0 is latched and stored into the lower 18 bit write data register provided BWS 1 0 are both assert...

Page 9: ...ck frequency During power up when the DOFF is tied HIGH the PLL is locked after 20 s of stable clock The PLL can also be reset by slowing or stopping the input clocks K and K for a minimum of 30 ns Ho...

Page 10: ...te D 8 0 is written into the device D 17 9 remains unaltered H L L H During the data portion of a write sequence CY7C1510KV18 only the upper nibble D 7 4 is written into the device D 3 0 remains unalt...

Page 11: ...nto the device D 35 9 remains unaltered L H H H L H During the data portion of a write sequence only the lower byte D 8 0 is written into the device D 35 9 remains unaltered H L H H L H During the dat...

Page 12: ...falling edge of TCK Instruction Register Three bit instructions are serially loaded into the instruction register This register is loaded when it is placed between the TDI and TDO pins as shown in TAP...

Page 13: ...egister After the data is captured it is possible to shift out the data by putting the TAP into the Shift DR state This places the boundary scan register between the TDI and TDO pins PRELOAD places an...

Page 14: ...ontroller follows 9 TEST LOGIC RESET TEST LOGIC IDLE SELECT DR SCAN CAPTURE DR SHIFT DR EXIT1 DR PAUSE DR EXIT2 DR UPDATE DR 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 1 0 SELECT IR S...

Page 15: ...t HIGH Voltage 0 65VDD VDD 0 3 V VIL Input LOW Voltage 0 3 0 35VDD V IX Input and Output Load Current GND VI VDD 5 5 A 0 0 1 2 29 30 31 Boundary Scan Register Identification Register 0 1 2 108 0 1 2 I...

Page 16: ...tTDIH TDI Hold after Clock Rise 5 ns tCH Capture Hold after Clock Rise 5 ns Output Times tTDOV TCK Clock LOW to TDO Valid 10 ns tTDOX TCK Clock LOW to TDO Invalid 0 ns TAP Timing and Test Conditions...

Page 17: ...9 Instruction Codes Instruction Code Description EXTEST 000 Captures the input and output ring contents IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and...

Page 18: ...L 7 8P 35 10E 63 2A 91 3L 8 9R 36 10D 64 1A 92 1M 9 11P 37 9E 65 2B 93 1L 10 10P 38 10C 66 3B 94 3N 11 10N 39 11D 67 1C 95 3M 12 9P 40 9C 68 1B 96 1N 13 10M 41 9D 69 3D 97 2M 14 11N 42 11B 70 3C 98 3P...

Page 19: ...and clock K K for 20 s to lock the PLL PLL Constraints PLL uses K clock as its synchronizing input The input must have low phase jitter which is specified as tKC Var The PLL functions at frequencies d...

Page 20: ...put HIGH Voltage Note 16 VDDQ 2 0 12 VDDQ 2 0 12 V VOL Output LOW Voltage Note 17 VDDQ 2 0 12 VDDQ 2 0 12 V VOH LOW Output HIGH Voltage IOH 0 1 mA Nominal Impedance VDDQ 0 2 VDDQ V VOL LOW Output LOW...

Page 21: ...tic 333 MHz x8 290 mA x9 290 x18 290 x36 290 300 MHz x8 280 mA x9 280 x18 280 x36 280 250 MHz x8 270 mA x9 270 x18 270 x36 270 200 MHz x8 250 mA x9 250 x18 250 x36 250 167 MHz x8 250 mA x9 250 x18 250...

Page 22: ...t Test conditions follow standard test methods and procedures for measuring thermal impedance in accordance with EIA JESD51 13 7 C W JC Thermal Resistance Junction to Case 3 73 C W Figure 4 AC Test Lo...

Page 23: ...to K Clock Rise 0 4 0 4 0 5 0 6 0 7 ns tSC tIVKH Control Setup to K Clock Rise RPS WPS 0 4 0 4 0 5 0 6 0 7 ns tSCDDR tIVKH DDR Control Setup to Clock K K Rise BWS0 BWS1 BWS2 BWS3 0 3 0 3 0 35 0 4 0 5...

Page 24: ...Clock C C Rise to High Z Active to High Z 24 25 0 45 0 45 0 45 0 45 0 50 ns tCLZ tCHQX1 Clock C C Rise to Low Z 24 25 0 45 0 45 0 45 0 45 0 50 ns PLL Timing tKC Var tKC Var Clock Phase Jitter 0 20 0 2...

Page 25: ...0 D51 D61 D31 D11 D10 D60 Q C C DON T CARE UNDEFINED t CQ CQ tKHCH tCO tKHCH tCLZ CHZ tKH tKL Q00 Q01 Q20 tKHKH tCYC Q21 Q40 Q41 tCQD tDOH tCCQO tCQOH tCCQO tCQOH tCQDOH tCQH tCQHCQH Notes 26 Q00 refe...

Page 26: ...13 x 15 x 1 4 mm Commercial CY7C1525KV18 333BZC CY7C1512KV18 333BZC CY7C1514KV18 333BZC CY7C1510KV18 333BZXC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free CY7C1525KV18 333BZXC...

Page 27: ...ay 13 x 15 x 1 4 mm Pb Free CY7C1525KV18 250BZXI CY7C1512KV18 250BZXI CY7C1514KV18 250BZXI 200 CY7C1510KV18 200BZC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Commercial CY7C1525KV18...

Page 28: ...rray 13 x 15 x 1 4 mm Pb Free CY7C1525KV18 167BZXC CY7C1512KV18 167BZXC CY7C1514KV18 167BZXC CY7C1510KV18 167BZI 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Industrial CY7C1525KV18 1...

Page 29: ...A B 0 05 M C B A 0 15 4X 0 35 0 06 SEATING PLANE 0 53 0 05 0 25 C 0 15 C PIN 1 CORNER TOP VIEW BOTTOM VIEW 2 3 4 5 6 7 8 9 10 10 00 14 00 B C D E F G H J K L M N 11 11 10 9 8 6 7 5 4 3 2 1 P R P R K M...

Page 30: ...RCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out...

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