Cypress Semiconductor CY7C1471V33 Specification Sheet Download Page 1

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72-Mbit (2M x 36/4M x 18/1M x 72)

Flow-Through SRAM with NoBL™ Architecture

CY7C1471V33
CY7C1473V33
CY7C1475V33

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Document #: 38-05288 Rev. *J

Revised July 04, 2007

Features

• No Bus Latency™ (NoBL™) architecture eliminates dead

cycles between write and read cycles

• Supports up to 133 MHz bus operations with zero wait states
• Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT™ devices
• Internally self timed output buffer control to eliminate the

need to use OE

• Registered inputs for flow through operation
• Byte Write capability
• 3.3V/2.5V IO supply (V

DDQ

)

• Fast clock-to-output times

— 6.5 ns (for 133-MHz device)

• Clock Enable (CEN) pin to enable clock and suspend

operation

• Synchronous self timed writes
• Asynchronous Output Enable (OE)
• CY7C1471V33, CY7C1473V33 available in

JEDEC-standard Pb-free 100-Pin TQFP, Pb-free and

non-Pb-free 165-Ball FBGA package. CY7C1475V33

available in Pb-free and non-Pb-free 209-Ball FBGA

package

• Three Chip Enables (CE

, CE

) for simple depth

expansion

• Automatic power down feature available using ZZ mode or

CE deselect

• IEEE 1149.1 JTAG Boundary Scan compatible
• Burst Capability — linear or interleaved burst order
• Low standby power

Functional Description

[1]

The CY7C1471V33, CY7C1473V33 and CY7C1475V33 are

3.3V, 2M x 36/4M x 18/1M x 72 synchronous flow through burst

SRAMs designed specifically to support unlimited true

back-to-back read or write operations without the insertion of

wait states. The CY7C1471V33, CY7C1473V33 and

CY7C1475V33 are equipped with the advanced No Bus

Latency (NoBL) logic required to enable consecutive read or

write operations with data being transferred on every clock

cycle. This feature dramatically improves the throughput of

data through the SRAM, especially in systems that require

frequent write-read transitions.
All synchronous inputs pass through input registers controlled

by the rising edge of the clock. The clock input is qualified by

the Clock Enable (CEN) signal, which when deasserted

suspends operation and extends the previous clock

cycle.Maximum access delay from the clock rise is 6.5 ns

(133-MHz device).
Write operations are controlled by two or four Byte Write Select

(BW

) and a Write Enable (WE) input. All writes are conducted

with on-chip synchronous self timed write circuitry.
Three synchronous Chip Enables (CE

, CE

) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output tri-state control. To avoid bus contention,

the output drivers are synchronously tri-stated during the data

portion of a write sequence.

Selection Guide

133 MHz

117 MHz

Unit

Maximum Access Time

6.5

8.5

Maximum Operating Current

305

275

Maximum CMOS Standby Current

120

Note

1. For best practice recommendations, refer to the Cypress application note

AN1064, SRAM System Guidelines

[+] Feedback

Summary of Contents for CY7C1471V33

Page 1: ... 3V 2M x 36 4M x 18 1M x 72 synchronous flow through burst SRAMs designed specifically to support unlimited true back to back read or write operations without the insertion of wait states The CY7C1471V33 CY7C1473V33 and CY7C1475V33 are equipped with the advanced No Bus Latency NoBL logic required to enable consecutive read or write operations with data being transferred on every clock cycle This f...

Page 2: ...IC A0 A1 D1 D0 Q1 Q0 A0 A1 ADV LD CE ADV LD C CLK CEN WRITE DRIVERS D A T A S T E E R I N G S E N S E A M P S WRITE ADDRESS REGISTER A0 A1 A O U T P U T B U F F E R S E ZZ SLEEP CONTROL C MODE BWA BWB WE CE1 CE2 CE3 OE READ LOGIC DQs DQPA DQPB MEMORY ARRAY E INPUT REGISTER ADDRESS REGISTER WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC BURST LOGIC A0 A1 D1 D0 Q1 Q0 A0 A1 ADV LD CE ADV LD C CLK CE...

Page 3: ...A T A S T E E R I N G O U T P U T B U F F E R S MEMORY ARRAY E E INPUT REGISTER 0 ADDRESS REGISTER 0 WRITE ADDRESS REGISTER 1 BURST LOGIC A0 A1 D1 D0 Q1 Q0 A0 A1 C ADV LD ADV LD E INPUT REGISTER 1 S E N S E A M P S O U T P U T R E G I S T E R S E CLK CEN WRITE DRIVERS BW a BW b WE ZZ BW c BW d BW e BW f BW g BW h Sleep Control WRITE ADDRESS REGISTER 2 WRITE REGISTRY AND DATA COHERENCY CONTROL LOGI...

Page 4: ...QC VSS VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSS DQD DQD DQD DQD VSS VDDQ DQD DQD DQPD A A CE 1 CE 2 BW D BW C BW B BW A CE 3 V DD V SS CLK WE CEN OE A A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 ...

Page 5: ...NC DQB DQB VSS VDDQ DQB DQB NC VDD NC VSS DQB DQB VDDQ VSS DQB DQB DQPB NC VSS VDDQ NC NC NC A A CE 1 CE 2 NC NC BW B BW A CE 3 V DD V SS CLK WE CEN OE A A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 ...

Page 6: ...B VDDQ VDD DQB DQB DQB NC DQB NC DQA DQA VDD VDDQ VDD VDDQ DQB VDD NC VDD DQA VDD VDDQ DQA VDDQ VDD VDD VDDQ VDD VDDQ DQA VDDQ A A VSS A A A DQB DQB DQB ZZ DQA DQA DQPA DQA A VDDQ A A0 A VSS NC A A 2 3 4 5 6 7 1 A B C D E F G H J K L M N P R TDO NC 576M NC 1G NC NC DQPB NC DQB CE1 NC CE3 BWB CEN A CE2 NC DQB DQB MODE NC DQB DQB NC NC NC A VDDQ NC BWA CLK WE VSS VSS VSS VSS VDDQ VSS VDD VSS VSS VSS...

Page 7: ...DQPb DQf DQf DQf DQf NC DQa DQa DQa DQa DQPe DQe DQe DQe DQe A A A A NC NC NC 144M A A NC 288M A A A A A A A1 A0 A A A A A A NC 576M NC NC NC NC NC BWSb BWSf BWSe BWSa BWSc BWSg BWSd BWSh TMS TDI TDO TCK NC NC MODE NC CEN VSS NC CLK NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS NC 1G VDD NC OE CE3 CE1 CE2 ADV LD WE VSS VSS VSS VSS VSS VSS VSS ZZ VSS VSS...

Page 8: ...ns are enabled to behave as outputs When deasserted HIGH IO pins are tri stated and act as input data pins OE is masked during the data portion of a write sequence during the first clock when emerging from a deselected state when the device is deselected CEN Input Synchronous Clock Enable Input Active LOW When asserted LOW the Clock signal is recognized by the SRAM When deasserted HIGH the Clock s...

Page 9: ...ounter that enables the user to supply a single address and conduct up to four reads without reasserting the address inputs ADV LD must be driven LOW to load a new address into the SRAM as described in the Single Read Access section The sequence of the burst counter is determined by the MODE input signal A LOW input on MODE selects a linear burst mode a HIGH selects an inter leaved burst sequence ...

Page 10: ...ress as described in the Single Write Access section When ADV LD is driven HIGH on the subsequent clock rise the Chip Enables CE1 CE2 and CE3 and WE inputs are ignored and the burst counter is incre mented The correct BWX inputs must be driven in each cycle of the burst write to write the correct bytes of data Sleep Mode The ZZ input pin is an asynchronous input Asserting ZZ places the SRAM in a p...

Page 11: ... L H L L L L H X L L H Tri State Write Abort Continue Burst Next X X X L H X H X L L H Tri State Ignore Clock Edge Stall Current X X X L X X X X H L H Sleep Mode None X X X H X X X X X X Tri State Notes 2 X Don t Care H Logic HIGH L Logic LOW BWX L signifies at least one Byte Write Select is active BWX Valid signifies that the desired Byte Write Selects are asserted see Truth Table for Read Write ...

Page 12: ...L L L Truth Table for Read Write The read write truth table for CY7C1473V33 follows 2 3 9 Function WE BWb BWa Read H X X Write No Bytes Written L H H Write Byte a DQa and DQPa L H L Write Byte b DQb and DQPb L L H Write Both Bytes L L L Truth Table for Read Write The read write truth table for CY7C1475V33 follows 2 3 9 Function WE BWx Read H X Write No Bytes Written L H Write Byte X DQx and DQPx L...

Page 13: ... to the TAP controller and is sampled on the rising edge of TCK It is allowable to leave this ball unconnected if the TAP is not used The ball is pulled up internally resulting in a logic HIGH level Test Data In TDI The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers The register between TDI and TDO is chosen by the instru...

Page 14: ...VED and must not be used The other five instructions are described in detail below The TAP controller used in this SRAM is not fully compliant to the 1149 1 convention because some of the mandatory 1149 1 instructions are not fully implemented The TAP controller cannot be used to load address data or control signals into the SRAM and cannot preload the IO buffers The SRAM does not implement the 11...

Page 15: ...is captured it is possible to shift out the data by putting the TAP into the Shift DR state This places the boundary scan register between the TDI and TDO balls Note that since the PRELOAD part of the command is not implemented putting the TAP to the Update DR state while performing a SAMPLE PRELOAD instruction has the same effect as the Pause DR command BYPASS When the BYPASS instruction is loade...

Page 16: ...ock LOW to TDO Valid 5 ns tTDOX TCK Clock LOW to TDO Invalid 0 ns Setup Times tTMSS TMS Setup to TCK Clock Rise 5 ns tTDIS TDI Setup to TCK Clock Rise 5 ns tCS Capture Setup to TCK Rise 5 ns Hold Times tTMSH TMS Hold after TCK Clock Rise 5 ns tTDIH TDI Hold after Clock Rise 5 ns tCH Capture Hold after Clock Rise 5 ns Notes 10 tCS and tCH refer to the setup and hold time requirements of latching da...

Page 17: ... TAP AC Output Load Equivalent TDO 1 25V 20pF Z 50Ω O 50Ω TAP DC Electrical Characteristics And Operating Conditions 0 C TA 70 C VDD 3 3V 0 165V unless otherwise noted 12 Parameter Description Test Conditions Min Max Unit VOH1 Output HIGH Voltage IOH 4 0 mA VDDQ 3 3V 2 4 V IOH 1 0 mA VDDQ 2 5V 2 0 V VOH2 Output HIGH Voltage IOH 100 µA VDDQ 3 3V 2 9 V VDDQ 2 5V 2 1 V VOL1 Output LOW Voltage IOL 8 0...

Page 18: ...XTEST 000 Captures IO ring contents Places the boundary scan register between TDI and TDO Forces all SRAM outputs to High Z state This instruction is not 1149 1 compliant IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO This operation does not affect SRAM operations SAMPLE Z 010 Captures IO ring contents Places the boundary scan register between ...

Page 19: ... 31 P10 51 G10 71 B2 12 L1 32 R9 52 F10 13 J2 33 R10 53 E10 14 M1 34 R11 54 A9 15 N1 35 N11 55 B9 16 K2 36 M11 56 A10 17 L2 37 L11 57 B10 18 M2 38 M10 58 A8 19 R1 39 L10 59 B8 20 R2 40 K11 60 A7 Boundary Scan Exit Order 4M x 18 Bit 165 Ball ID Bit 165 Ball ID Bit 165 Ball ID Bit 165 Ball ID 1 D2 14 R4 27 L10 40 B10 2 E2 15 P6 28 K10 41 A8 3 F2 16 R6 29 J10 42 B8 4 G2 17 R8 30 H11 43 A7 5 J1 18 P3 ...

Page 20: ...1 A9 8 D2 36 W2 64 N11 92 U8 9 E1 37 T6 65 N10 93 A6 10 E2 38 V3 66 M11 94 D6 11 F1 39 V4 67 M10 95 K6 12 F2 40 U4 68 L11 96 B6 13 G1 41 W5 69 L10 97 K3 14 G2 42 V6 70 P6 98 A8 15 H1 43 W6 71 J11 99 B4 16 H2 44 V5 72 J10 100 B3 17 J1 45 U5 73 H11 101 C3 18 J2 46 U6 74 H10 102 C4 19 L1 47 W7 75 G11 103 C8 20 L2 48 V7 76 G10 104 C9 21 M1 49 U7 77 F11 105 B9 22 M2 50 V8 78 F10 106 B8 23 N1 51 V9 79 E...

Page 21: ... 3 3V IO 2 0 VDD 0 3V V For 2 5V IO 1 7 VDD 0 3V V VIL Input LOW Voltage 14 For 3 3V IO 0 3 0 8 V For 2 5V IO 0 3 0 7 V IX Input Leakage Current except ZZ and MODE GND VI VDDQ 5 5 µA Input Current of MODE Input VSS 30 µA Input VDD 5 µA Input Current of ZZ Input VSS 5 µA Input VDD 30 µA IOZ Output Leakage Current GND VI VDD Output Disabled 5 5 µA IDD VDD Operating Supply Current VDD Max IOUT 0 mA f...

Page 22: ...nd after any design or process change that may affect these parameters Parameter Description Test Conditions 100 TQFP Max 165 FBGA Max 209 FBGA Max Unit ΘJA Thermal Resistance Junction to Ambient Test conditions follow standard test methods and procedures for measuring thermal impedance according to EIA JESD51 24 63 16 3 15 2 C W ΘJC Thermal Resistance Junction to Case 2 28 2 1 1 7 C W AC Test Loa...

Page 23: ...re CLK Rise 1 5 1 5 ns tDS Data Input Setup Before CLK Rise 1 5 1 5 ns tCES Chip Enable Setup Before CLK Rise 1 5 1 5 ns Hold Times tAH Address Hold After CLK Rise 0 5 0 5 ns tALH ADV LD Hold After CLK Rise 0 5 0 5 ns tWEH WE BWX Hold After CLK Rise 0 5 0 5 ns tCENH CEN Hold After CLK Rise 0 5 0 5 ns tDH Data Input Hold After CLK Rise 0 5 0 5 ns tCEH Chip Enable Hold After CLK Rise 0 5 0 5 ns Note...

Page 24: ...OMMAND tCLZ D A1 D A2 Q A4 Q A3 D A2 1 tDOH tCHZ tCDV WRITE D A2 BURST WRITE D A2 1 READ Q A3 READ Q A4 BURST READ Q A4 1 WRITE D A5 READ Q A6 WRITE D A7 DESELECT OE tOEV tOELZ tOEHZ DON T CARE UNDEFINED D A5 tDOH Q A4 1 D A7 Q A6 Notes 20 For this waveform ZZ is tied LOW 21 When CE is LOW CE1 is LOW CE2 is HIGH and CE3 is LOW When CE is HIGH CE1 is HIGH CE2 is LOW or CE3 is HIGH 22 Order of the B...

Page 25: ...s continued READ Q A3 4 5 6 7 8 9 10 A3 A4 A5 D A4 1 2 3 CLK CE WE CEN BW A D ADV LD ADDRESS DQ COMMAND WRITE D A4 STALL WRITE D A1 READ Q A2 STALL NOP READ Q A5 DESELECT CONTINUE DESELECT DON T CARE UNDEFINED tCHZ A1 A2 Q A2 D A1 Q A3 tDOH Q A5 Note 23 The IGNORE CLOCK EDGE or STALL cycle Clock 3 illustrates CEN being used to create a pause A write is not performed during this cycle Feedback ...

Page 26: ...Switching Waveforms continued t ZZ I SUPPLY CLK ZZ tZZREC ALL INPUTS except ZZ DON T CARE I DDZZ tZZI tRZZI Outputs Q High Z DESELECT or READ Only Notes 24 Device must be deselected when entering ZZ mode See Truth Table on page 11 for all possible signal conditions to deselect the device 25 DQs are in high Z when exiting ZZ sleep mode Feedback ...

Page 27: ...CY7C1471V33 133BZXI 51 85165 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Pb Free CY7C1473V33 133BZXI CY7C1475V33 133BGI 51 85167 209 Ball Fine Pitch Ball Grid Array 14 22 1 76 mm CY7C1475V33 133BGXI 209 Ball Fine Pitch Ball Grid Array 14 22 1 76 mm Pb Free 117 CY7C1471V33 117AXC 51 85050 100 Pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Pb Free Commercial CY7C1473V33 117AXC CY7C1471V33 117BZC ...

Page 28: ...SION END FLASH SHALL NOT EXCEED 0 0098 in 0 25 mm PER SIDE 3 DIMENSIONS IN MILLIMETERS BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 0 30 0 08 0 65 20 00 0 10 22 00 0 20 1 40 0 05 12 1 1 60 MAX 0 05 MIN 0 60 0 15 0 MIN 0 25 0 7 8X STAND OFF R 0 08 MIN TYP 0 20 MAX 0 15 MAX 0 20 MAX R 0 08 MIN 0 20 MAX 14 00 0 10 16 00 0 20 0 10 SEE DETAIL A DETAIL A 1 100 30 0 5 1 3 51 8...

Page 29: ... A 1 PIN 1 CORNER 17 00 0 10 15 00 0 10 7 00 1 00 Ø0 45 0 05 165X Ø0 25 M C A B Ø0 05 M C B A 0 15 4X 0 35 1 40 MAX SEATING PLANE 0 53 0 05 0 25 C 0 15 C PIN 1 CORNER TOP VIEW BOTTOM VIEW 2 3 4 5 6 7 8 9 10 10 00 14 00 B C D E F G H J K L M N 11 11 10 9 8 6 7 5 4 3 2 1 P R P R K M N L J H G F E D C B A C 1 00 5 00 0 36 0 05 0 10 51 85165 A Feedback ...

Page 30: ...ress written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifie...

Page 31: ...ge 21 E 299511 See ECN SYT Removed 117 MHz Speed Bin Changed ΘJA from 16 8 to 24 63 C W and ΘJC from 3 3 to 2 28 C W for 100 TQFP Package on Page 21 Added Pb free information for 100 Pin TQFP 165 FBGA and 209 BGA Packages Added comment of Pb free BG packages availability below the Ordering Information F 320197 See ECN PCI Corrected part number typos in the logic block diagram on page 2 G 331513 Se...

Page 32: ...Relative to GND Changed tTH tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC Switching Characteristics table Updated the Ordering Information table J 1274732 See ECN VKN AESA Corrected typo in the NOP STALL and DESELECT Cycles waveform Document Title CY7C1471V33 CY7C1473V33 CY7C1475V33 72 Mbit 2M x 36 4M x 18 1M x 72 Flow Through SRAM with NoBL Architecture Document Number 38 05288 R...

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