Cypress Semiconductor CY7C1471BV33 Specification Sheet Download Page 26

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CY7C1471BV33

CY7C1473BV33, CY7C1475BV33

Document #: 001-15029 Rev. *B

Page 26 of 32

Figure 6

shows NOP, STALL and DESELECT Cycles waveform.

[20, 21, 23]

Figure 6. NOP, STALL, and DESELECT Cycles

Switching Waveforms

(continued)

READ

Q(A3)

D(A4)

CLK

CEN

[A:D]

ADV/LD

ADDRESS

COMMAND

WRITE

D(A4)

STALL

WRITE

D(A1)

READ

Q(A2)

STALL

NOP

READ

Q(A5)

DESELECT

CONTINUE

DESELECT

DON’T CARE

UNDEFINED

tCHZ

Q(A2)

D(A1)

Q(A3)

tDOH

Q(A5)

Note

23. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle.

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Summary of Contents for CY7C1471BV33

Page 1: ...V 2M x 36 4M x 18 1M x 72 synchronous flow through burst SRAMs designed specifically to support unlimited true back to back read or write operations without the insertion of wait states The CY7C1471BV...

Page 2: ...OGIC A0 A1 D1 D0 Q1 Q0 A0 A1 ADV LD CE ADV LD C CLK CEN WRITE DRIVERS D A T A S T E E R I N G S E N S E A M P S WRITE ADDRESS REGISTER A0 A1 A O U T P U T B U F F E R S E ZZ SLEEP CONTROL C MODE BWA B...

Page 3: ...D A T A S T E E R I N G O U T P U T B U F F E R S MEMORY ARRAY E E INPUT REGISTER 0 ADDRESS REGISTER 0 WRITE ADDRESS REGISTER 1 BURST LOGIC A0 A1 D1 D0 Q1 Q0 A0 A1 C ADV LD ADV LD E INPUT REGISTER 1 S...

Page 4: ...DD NC VSS DQD DQD VDDQ VSS DQD DQD DQD DQD VSS VDDQ DQD DQD DQPD A A CE 1 CE 2 BW D BW C BW B BW A CE 3 V DD V SS CLK WE CEN OE A A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26...

Page 5: ...QB NC VDD NC VSS DQB DQB VDDQ VSS DQB DQB DQPB NC VSS VDDQ NC NC NC A A CE 1 CE 2 NC NC BW B BW A CE 3 V DD V SS CLK WE CEN OE A A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26...

Page 6: ...QPB VDDQ VDD DQB DQB DQB NC DQB NC DQA DQA VDD VDDQ VDD VDDQ DQB VDD NC VDD DQA VDD VDDQ DQA VDDQ VDD VDD VDDQ VDD VDDQ DQA VDDQ A A VSS A A A DQB DQB DQB ZZ DQA DQA DQPA DQA A VDDQ A A0 A VSS NC A A...

Page 7: ...DQPb DQf DQf DQf DQf NC DQa DQa DQa DQa DQPe DQe DQe DQe DQe A A A A NC NC NC 144M A A NC 288M A A A A A A A1 A0 A A A A A A NC 576M NC NC NC NC NC BWSb BWSf BWSe BWSa BWSc BWSg BWSd BWSh TMS TDI TDO...

Page 8: ...o behave as outputs When deasserted HIGH IO pins are tri stated and act as input data pins OE is masked during the data portion of a write sequence during the first clock when emerging from a deselect...

Page 9: ...ffers are controlled by OE and the internal control logic OE must be driven LOW to drive out the requested data On the subsequent clock another operation read write deselect can be initiated When the...

Page 10: ...on DQs and DQPX are automatically tri stated during the data portion of a write cycle regardless of the state of OE Burst Write Accesses The CY7C1471BV33 CY7C1473BV33 and CY7C1475BV33 have an on chip...

Page 11: ...L L L L H X L L H Tri State Write Abort Continue Burst Next X X X L H X H X L L H Tri State Ignore Clock Edge Stall Current X X X L X X X X H L H Sleep Mode None X X X H X X X X X X Tri State Notes 1...

Page 12: ...L L L The read write truth table for CY7C1473BV33 follows 1 2 8 Truth Table for Read Write Function WE BWa BWb Read H X X Write No Bytes Written L H H Write Byte a DQa and DQPa L L H Write Byte b DQb...

Page 13: ...ted to the least significant bit LSB of any register See TAP Controller State Diagram on page 15 Performing a TAP Reset A RESET is performed by forcing TMS HIGH VDD for five rising edges of TCK This R...

Page 14: ...nstruction causes the boundary scan register to be connected between the TDI and TDO balls when the TAP controller is in a Shift DR state It also places all SRAM outputs into a High Z state SAMPLE PRE...

Page 15: ...TAP Controller State Diagram TEST LOGIC RESET RUN TEST IDLE SELECT DR SCAN SELECT IR SCAN CAPTURE DR SHIFT DR CAPTURE IR SHIFT IR EXIT1 DR PAUSE DR EXIT1 IR PAUSE IR EXIT2 DR UPDATE DR EXIT2 IR UPDAT...

Page 16: ...15029 Rev B Page 16 of 32 TAP Controller Block Diagram Bypass Register 0 Instruction Register 0 1 2 Identification Register 0 1 2 29 30 31 Boundary Scan Register 0 1 2 x Selection Circuitry TCK TMS T...

Page 17: ...5V TAP AC Output Load Equivalent TDO 1 25V 20pF Z 50 O 50 TAP DC Electrical Characteristics and Operating Conditions 0 C TA 70 C VDD 3 3V 0 165V unless otherwise noted 9 Parameter Description Test Co...

Page 18: ...ns Setup Times tTMSS TMS Setup to TCK Clock Rise 5 ns tTDIS TDI Setup to TCK Clock Rise 5 ns tCS Capture Setup to TCK Rise 5 ns Hold Times tTMSH TMS Hold after TCK Clock Rise 5 ns tTDIH TDI Hold afte...

Page 19: ...EXTEST 000 Captures IO ring contents Places the boundary scan register between TDI and TDO Forces all SRAM outputs to High Z state This instruction is not 1149 1 compliant IDCODE 001 Loads the ID reg...

Page 20: ...1 31 P10 51 G10 71 B2 12 L1 32 R9 52 F10 13 J2 33 R10 53 E10 14 M1 34 R11 54 A9 15 N1 35 N11 55 B9 16 K2 36 M11 56 A10 17 L2 37 L11 57 B10 18 M2 38 M10 58 A8 19 R1 39 L10 59 B8 20 R2 40 K11 60 A7 Boun...

Page 21: ...91 A9 8 D2 36 W2 64 N11 92 U8 9 E1 37 T6 65 N10 93 A6 10 E2 38 V3 66 M11 94 D6 11 F1 39 V4 67 M10 95 K6 12 F2 40 U4 68 L11 96 B6 13 G1 41 W5 69 L10 97 K3 14 G2 42 V6 70 P6 98 A8 15 H1 43 W6 71 J11 99...

Page 22: ...1 7 VDD 0 3V V VIL Input LOW Voltage 13 For 3 3V IO 0 3 0 8 V For 2 5V IO 0 3 0 7 V IX Input Leakage Current except ZZ and MODE GND VI VDDQ 5 5 A Input Current of MODE Input VSS 30 A Input VDD 5 A Inp...

Page 23: ...and after any design or process change that may affect these parameters Parameter Description Test Conditions 100 TQFP Max 165 FBGA Max 209 FBGA Max Unit JA Thermal Resistance Junction to Ambient Tes...

Page 24: ...Before CLK Rise 1 5 1 5 ns tDS Data Input Setup Before CLK Rise 1 5 1 5 ns tCES Chip Enable Setup Before CLK Rise 1 5 1 5 ns Hold Times tAH Address Hold After CLK Rise 0 5 0 5 ns tALH ADV LD Hold Aft...

Page 25: ...COMMAND tCLZ D A1 D A2 Q A4 Q A3 D A2 1 tDOH tCHZ tCDV WRITE D A2 BURST WRITE D A2 1 READ Q A3 READ Q A4 BURST READ Q A4 1 WRITE D A5 READ Q A6 WRITE D A7 DESELECT OE tOEV tOELZ tOEHZ DON T CARE UNDEF...

Page 26: ...ms continued READ Q A3 4 5 6 7 8 9 10 A3 A4 A5 D A4 1 2 3 CLK CE WE CEN BW A D ADV LD ADDRESS DQ COMMAND WRITE D A4 STALL WRITE D A1 READ Q A2 STALL NOP READ Q A5 DESELECT CONTINUE DESELECT DON T CARE...

Page 27: ...forms continued t ZZ I SUPPLY CLK ZZ tZZREC ALL INPUTS except ZZ DON T CARE I DDZZ tZZI tRZZI Outputs Q High Z DESELECT or READ Only Notes 24 Device must be deselected when entering ZZ mode See the Th...

Page 28: ...3BZI CY7C1471BV33 133BZXI 51 85165 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Pb Free CY7C1473BV33 133BZXI CY7C1475BV33 133BGI 51 85167 209 Ball Fine Pitch Ball Grid Array 14 22 1 76 mm CY7C...

Page 29: ...N END FLASH SHALL NOT EXCEED 0 0098 in 0 25 mm PER SIDE 3 DIMENSIONS IN MILLIMETERS BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 0 30 0 08 0 65 20 00 0 10 22 00 0 20 1 40 0...

Page 30: ...1 PIN 1 CORNER 17 00 0 10 15 00 0 10 7 00 1 00 0 45 0 05 165X 0 25 M C A B 0 05 M C B A 0 15 4X 0 35 1 40 MAX SEATING PLANE 0 53 0 05 0 25 C 0 15 C PIN 1 CORNER TOP VIEW BOTTOM VIEW 2 3 4 5 6 7 8 9 1...

Page 31: ...CY7C1471BV33 CY7C1473BV33 CY7C1475BV33 Document 001 15029 Rev B Page 31 of 32 Figure 10 209 Ball FBGA 14 x 22 x 1 76 mm Package Diagrams continued 51 85167 Feedback...

Page 32: ...ve works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with...

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