Cypress Semiconductor CY7C1392BV18 Specification Sheet Download Page 28

Page: 28 / 31

CY7C1392BV18, CY7C1992BV18
CY7C1393BV18, CY7C1394BV18

Document #: 38-05623 Rev. *D

Page 28 of 31

167

CY7C1392BV18-167BZC

51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)

Commercial

CY7C1992BV18-167BZC

CY7C1393BV18-167BZC

CY7C1394BV18-167BZC

CY7C1392BV18-167BZXC

51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1992BV18-167BZXC

CY7C1393BV18-167BZXC

CY7C1394BV18-167BZXC

CY7C1392BV18-167BZI

51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)

Industrial

CY7C1992BV18-167BZI

CY7C1393BV18-167BZI

CY7C1394BV18-167BZI

CY7C1392BV18-167BZXI

51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1992BV18-167BZXI

CY7C1393BV18-167BZXI

CY7C1394BV18-167BZXI

Ordering Information

(continued)

Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or
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www.cypress.com

for actual products offered.

Speed

(MHz)

Ordering Code

Package
Diagram

Package Type

Operating

Range

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Summary of Contents for CY7C1392BV18

Page 1: ...te port has data inputs to support write operations The DDR II SIO has separate data inputs and data outputs to completely eliminate the need to turn around the data bus required with common IO device...

Page 2: ...Decode Read Data Reg LD Q 7 0 Reg Reg Reg 8 8 16 8 NWS 1 0 VREF Write Add Decode Write Data Reg 8 8 20 8 R W LD R W CQ CQ DOFF 1M x 8 Array Write Data Reg Control Logic C C 1M x 9 Array CLK A 19 0 Ge...

Page 3: ...d Data Reg LD Q 17 0 Reg Reg Reg 18 36 18 BWS 1 0 VREF Write Add Decode Write Data Reg 18 18 19 18 R W LD R W CQ CQ DOFF 512K x 18 Array Write Data Reg Control Logic C C 18 256K x 36 Array CLK A 17 0...

Page 4: ...VSS VSS VSS VDDQ NC NC Q0 M NC NC NC VSS VSS VSS VSS VSS NC NC D0 N NC D7 NC VSS A A A VSS NC NC NC P NC NC Q7 A A C A A NC NC NC R TDO TCK A A A C A A A TMS TDI CY7C1992BV18 2M x 9 1 2 3 4 5 6 7 8 9...

Page 5: ...C D0 Q0 R TDO TCK A A A C A A A TMS TDI CY7C1394BV18 512K x 36 1 2 3 4 5 6 7 8 9 10 11 A CQ NC 288M NC 72M R W BWS2 K BWS1 LD NC 36M NC 144M CQ B Q27 Q18 D18 A BWS3 K BWS0 A D17 Q17 Q8 C D27 Q28 D19 V...

Page 6: ...tions Internally the device is organized as 2M x 8 2 arrays each of 1M x 8 for CY7C1392BV18 2M x 9 2 arrays each of 1M x 9 for CY7C1992BV18 1M x 18 2 arrays each of 512K x 18 for CY7C1393BV18 and 512K...

Page 7: ...nnected directly to VDDQ which enables the minimum impedance mode This pin cannot be connected directly to GND or left unconnected DOFF Input DLL Turn Off Active LOW Connecting this pin to ground turn...

Page 8: ...k K This pipelines the data flow such that 18 bits of data can be transferred into the device on every rising edge of the input clocks K and K When Write access is deselected the device ignores all in...

Page 9: ...024 clock cycles after a stable clock is presented The DLL may be disabled by applying ground to the DOFF pin When the DLL is turned off the device behaves in DDR I mode with one cycle latency and a l...

Page 10: ...ten into the device D 17 9 remains unaltered H L L H During the data portion of a write sequence CY7C1392BV18 only the upper nibble D 7 4 is written into the device D 3 0 remains unaltered CY7C1393BV1...

Page 11: ...the device D 35 9 remains unaltered L H H H L H During the data portion of a write sequence only the lower byte D 8 0 is written into the device D 35 9 remains unaltered H L H H L H During the data p...

Page 12: ...edge of TCK Instruction Register Three bit instructions can be serially loaded into the instruction register This register is loaded when it is placed between the TDI and TDO pins as shown in TAP Con...

Page 13: ...scan register After the data is captured it is possible to shift out the data by putting the TAP into the Shift DR state This places the boundary scan register between the TDI and TDO pins PRELOAD pl...

Page 14: ...oller follows 9 TEST LOGIC RESET TEST LOGIC IDLE SELECT DR SCAN CAPTURE DR SHIFT DR EXIT1 DR PAUSE DR EXIT2 DR UPDATE DR 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 1 0 SELECT IR SCAN...

Page 15: ...GH Voltage 0 65VDD VDD 0 3 V VIL Input LOW Voltage 0 3 0 35VDD V IX Input and Output Load Current GND VI VDD 5 5 A 0 0 1 2 29 30 31 Boundary Scan Register Identification Register 0 1 2 106 0 1 2 Instr...

Page 16: ...IH TDI Hold after Clock Rise 5 ns tCH Capture Hold after Clock Rise 5 ns Output Times tTDOV TCK Clock LOW to TDO Valid 10 ns tTDOX TCK Clock LOW to TDO Invalid 0 ns TAP Timing and Test Conditions Figu...

Page 17: ...ruction Codes Instruction Code Description EXTEST 000 Captures the input and output ring contents IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO T...

Page 18: ...7 2K 7 8P 34 11E 61 4B 88 1K 8 9R 35 10E 62 3A 89 2L 9 11P 36 10D 63 1H 90 3L 10 10P 37 9E 64 1A 91 1M 11 10N 38 10C 65 2B 92 1L 12 9P 39 11D 66 3B 93 3N 13 10M 40 9C 67 1C 94 3M 14 11N 41 9D 68 1B 95...

Page 19: ...K K for 1024 cycles to lock the DLL DLL Constraints DLL uses K clock as its synchronizing input The input must have low phase jitter which is specified as tKC Var The DLL functions at frequencies dow...

Page 20: ...H Output HIGH Voltage Note 16 VDDQ 2 0 12 VDDQ 2 0 12 V VOL Output LOW Voltage Note 17 VDDQ 2 0 12 VDDQ 2 0 12 V VOH LOW Output HIGH Voltage IOH 0 1 mA Nominal Impedance VDDQ 0 2 VDDQ V VOL LOW Output...

Page 21: ...300 MHz x8 275 mA x9 275 x18 285 x36 300 278 MHz x8 265 mA x9 265 x18 275 x36 290 250 MHz x8 255 mA x9 255 x18 260 x36 275 200 MHz x8 245 mA x9 245 x18 250 x36 260 167 MHz x8 240 mA x9 240 x18 245 x36...

Page 22: ...tion to Ambient Test conditions follow standard test methods and procedures for measuring thermal impedance in accordance with EIA JESD51 18 7 C W JC Thermal Resistance Junction to Case 4 5 C W Figure...

Page 23: ...LD R W 0 4 0 4 0 5 0 6 0 7 ns tSCDDR tIVKH Double Data Rate Control Setup to Clock K K Rise BWS0 BWS1 BWS2 BWS3 0 3 0 3 0 35 0 4 0 5 ns tSD 23 tDVKH D X 0 Setup to Clock K K Rise 0 3 0 3 0 35 0 4 0 5...

Page 24: ...HQZ Clock C C Rise to High Z Active to High Z 24 25 0 45 0 45 0 45 0 45 0 50 ns tCLZ tCHQX1 Clock C C Rise to Low Z 24 25 0 45 0 45 0 45 0 45 0 50 ns DLL Timing tKC Var tKC Var Clock Phase Jitter 0 20...

Page 25: ...C tSA tHA tSD tHD tSD tHD tCLZ tDOH SC tKH tKHKH tKL tCYC tCQD tCCQO tCQOH tCCQO tCQOH DON T CARE UNDEFINED A0 A1 A2 A3 A4 D20 D21 D30 D31 Q40 Q11 Q10 Q41 Q00 Q01 tCQDOH tCHZ Notes 26 Q00 refers to ou...

Page 26: ...Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Industrial CY7C1992BV18 300BZI CY7C1393BV18 300BZI CY7C1394BV18 300BZI CY7C1392BV18 300BZXI 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb...

Page 27: ...250BZXI 200 CY7C1392BV18 200BZC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Commercial CY7C1992BV18 200BZC CY7C1393BV18 200BZC CY7C1394BV18 200BZC CY7C1392BV18 200BZXC 51 85180 165 B...

Page 28: ...8 167BZXC CY7C1392BV18 167BZI 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Industrial CY7C1992BV18 167BZI CY7C1393BV18 167BZI CY7C1394BV18 167BZI CY7C1392BV18 167BZXI 51 85180 165 Bal...

Page 29: ...0 05 M C B A 0 15 4X 0 35 0 06 SEATING PLANE 0 53 0 05 0 25 C 0 15 C PIN 1 CORNER TOP VIEW BOTTOM VIEW 2 3 4 5 6 7 8 9 10 10 00 14 00 B C D E F G H J K L M N 11 11 10 9 8 6 7 5 4 3 2 1 P R P R K M N L...

Page 30: ...anged C C Pin Description in the features section and Pin Description Added power up sequence details and waveforms Added foot notes 15 16 17 on page 18 Replaced Three state with Tri state Changed the...

Page 31: ...as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LI...

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