Cypress Semiconductor CY7C1386DV25 Specification Sheet Download Page 2

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CY7C1386DV25, CY7C1386FV25

CY7C1387DV25, CY7C1387FV25

Document Number: 38-05548 Rev. *E

Page 2 of 30

Logic Block Diagram – CY7C1386DV25/CY7C1386FV25

[3]

(512K x 36)

Logic Block Diagram – CY7C1387DV25/CY7C1387FV25

[3]

(1M x 18)

ADDRESS
REGISTER

ADV

CLK

BURST

COUNTER AND

LOGIC

CLR

ADSP

ADSC

MODE

BWE

DQP

BYTE

WRITE REGISTER

,DQP

BYTE

WRITE REGISTER

,DQP

BYTE

WRITE REGISTER

DQP

BYTE

WRITE REGISTER

ENABLE

PIPELINED

ENABLE

OUTPUT

REGISTERS

SENSE

AMPS

MEMORY

ARRAY

OUTPUT

BUFFERS

DQP

BYTE

WRITE DRIVER

,DQP

BYTE

WRITE DRIVER

,DQP

BYTE

WRITE DRIVER

DQP

BYTE

WRITE DRIVER

INPUT

REGISTERS

A0,A1,A

A[1:0]

CONTROL

DQs

DQP

ADDRESS
REGISTER

ADV

CLK

BURST

COUNTER AND

CLR

ADSC

DQP

BYTE

WRITE REGISTER

A ,

DQP

BYTE

WRITE REGISTER

ENABLE

SENSE

AMPS

MEMORY

ARRAY

ADSP

[1:0]

MODE

BWE

PIPELINED

ENABLE

DQP

OUTPUT

REGISTERS

INPUT

REGISTERS

OUTPUT

BUFFERS

B ,

DQP

BYTE

DQP

BYTE

SLEEP

CONTROL

A0, A1, A

Note

3. CY7C1386FV25 and CY7C1387FV25 have only 1 chip enable (CE

[+] Feedback

Summary of Contents for CY7C1386DV25

Page 1: ...l data inputs address pipelining chip enable CE1 depth expansion chip enables CE2 and CE3 2 burst control inputs ADSC ADSP and ADV write enables BWX and BWE and global write GW Asynchronous inputs inc...

Page 2: ...LINED ENABLE OUTPUT REGISTERS SENSE AMPS MEMORY ARRAY OUTPUT BUFFERS DQA DQP A BYTE WRITE DRIVER DQB DQP B BYTE WRITE DRIVER DQc DQP C BYTE WRITE DRIVER DQD DQP D BYTE WRITE DRIVER INPUT REGISTERS A0...

Page 3: ...68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 MODE CY7C1386DV25 512K X 36 NC A A A A A 1 A 0 NC 72M NC 36M V SS V DD A A A A A A A...

Page 4: ...C VDD DQD DQD DQD DQD ADSC NC CE1 OE ADV GW VSS VSS VSS VSS VSS VSS VSS VSS DQPA MODE DQPD DQPB BWB BWC NC VDD NC BWA NC BWE BWD ZZ 2 3 4 5 6 7 1 A B C D E F G H J K L M N P R T U VDDQ NC 288M NC 144M...

Page 5: ...Q VDD DQB DQB DQB NC DQB NC DQA DQA VDD VDDQ VDD VDDQ DQB VDD NC VDD DQA VDD VDDQ DQA VDDQ VDD VDD VDDQ VDD VDDQ DQA VDDQ A A VSS A A A DQB DQB DQB ZZ DQA DQA DQPA DQA A VDDQ A CY7C1387DV25 1M x 18 A0...

Page 6: ...ument for BGA CE3 is sampled only when a new external address is loaded OE Input Asynchronous Output enable asynchronous input active LOW Controls the direction of the IO pins When LOW the IO pins beh...

Page 7: ...exception occurs when the SRAM is emerging from a deselected state to a selected state its outputs are always tri stated during the first cycle of the access After the first cycle of the access the o...

Page 8: ...corresponding address location in the memory core If a byte write is conducted only the selected bytes are written Bytes not selected during a byte write operation will remain unaltered A synchronous...

Page 9: ...X H L H L L H Q READ Cycle Continue Burst Next H X X L X H L H H L H Tri State WRITE Cycle Continue Burst Next X X X L H H L L X L H D WRITE Cycle Continue Burst Next H X X L X H L L X L H D READ Cycl...

Page 10: ...te D DQD and DQPD H L L H H H Write Bytes D A H L L H H L Write Bytes D B H L L H L H Write Bytes D B A H L L H L L Write Bytes D C H L L L H H Write Bytes D C A H L L L H L Write Bytes D C B H L L L...

Page 11: ...o the input of any of the registers The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register For information on loading the instruction register s...

Page 12: ...uring this state instructions are shifted through the instruction register through the TDI and TDO balls To execute the instruction once it is shifted in the TAP controller needs to be moved into the...

Page 13: ...d into the preload register during the Update DR state in the TAP controller it will directly control the state of the output Q bus pins when the EXTEST is entered as the current instruction When HIGH...

Page 14: ...Setup to TCK Clock Rise 5 ns tCS Capture Setup to TCK Rise 5 ns Hold Times tTMSH TMS Hold after TCK Clock Rise 5 ns tTDIH TDI Hold after Clock Rise 5 ns tCH Capture Hold after Clock Rise 5 ns TDO 1 25...

Page 15: ...ID 32 32 Boundary Scan Order 119 ball BGA package 85 85 Boundary Scan Order 165 ball fBGA package 89 89 Identification Codes Instruction Code Description EXTEST 000 Captures IO ring contents Places t...

Page 16: ...B2 71 K1 6 L5 28 E6 50 B3 72 L2 7 R6 29 D6 51 A3 73 N2 8 U6 30 C7 52 C2 74 P2 9 R7 31 B7 53 A2 75 R3 10 T7 32 C6 54 B1 76 T1 11 P6 33 A6 55 C1 77 R1 12 N7 34 C5 56 D2 78 T2 13 M6 35 B5 57 E1 79 L3 14...

Page 17: ...37 A9 67 H3 8 P9 38 B9 68 J1 9 P10 39 C10 69 K1 10 R10 40 A8 70 L1 11 R11 41 B8 71 M1 12 H11 42 A7 72 J2 13 N11 43 B7 73 K2 14 M11 44 B6 74 L2 15 L11 45 A6 75 M2 16 K11 46 B5 76 N1 17 J11 47 A5 77 N2...

Page 18: ...DD 0 3V V VIL Input LOW Voltage 17 for 2 5V IO 0 3 0 7 V IX Input Leakage Current except ZZ and MODE GND VI VDDQ 5 5 A Input Current of MODE Input VSS 30 A Input VDD 5 A Input Current of ZZ Input VSS...

Page 19: ...Test Conditions 100 TQFP Package 119 BGA Package 165 FBGA Package Unit JA Thermal Resistance Junction to Ambient Test conditions follow standard test methods and procedures for measuring thermal impe...

Page 20: ...1 4 1 5 ns Hold Times tAH Address Hold After CLK Rise 0 3 0 4 0 5 ns tADH ADSP ADSC Hold After CLK Rise 0 3 0 4 0 5 ns tADVH ADV Hold After CLK Rise 0 3 0 4 0 5 ns tWEH GW BWE BWX Hold After CLK Rise...

Page 21: ...DQ High Z tDOH tCO ADV tOEHZ tCO SingleREAD BURSTREAD tOEV tOELZ tCHZ Burstwrapsaround toitsinitialstate tADVH tADVS tWEH tWES tADH tADS Q A2 Q A2 1 Q A2 2 Q A1 Q A2 Q A2 1 Q A3 Q A2 3 A2 A3 Deselect...

Page 22: ...DV BURST READ BURST WRITE D A2 D A2 1 D A3 D A3 1 D A2 3 A2 A3 Extended BURST WRITE Single WRITE tADH tADS tADH tADS t OEHZ tADVH tADVS tWEH tWES t DH t DS GW tWEH tWES Byte write signals are ignored...

Page 23: ...OE ADSC CE tAH tAS A2 tCEH tCES Data Out Q High Z ADV Single WRITE D A3 A4 A5 A6 D A5 D A6 Data In D BURST READ Back to Back READs High Z Q A2 Q A1 Q A4 tWEH tWES Q A4 3 tOEHZ tDH tDS tOELZ tCLZ tCO...

Page 24: ...continued t ZZ I SUPPLY CLK ZZ t ZZREC ALL INPUTS except ZZ DON T CARE I DDZZ t ZZI tRZZI Outputs Q High Z DESELECT or READ Only Notes 30 Device must be deselected when entering ZZ sleep mode See cyc...

Page 25: ...Ball Grid Array 14 x 22 x 2 4 mm Pb Free CY7C1387FV25 167BGXI CY7C1386DV25 167BZI 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1387DV25 167BZI CY7C1386DV25 167BZXI 51 85180 165 b...

Page 26: ...y 13 x 15 x 1 4 mm Pb Free CY7C1387DV25 250BZXC CY7C1386DV25 250AXI 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Pb Free Industrial CY7C1387DV25 250AXI CY7C1386FV25 250BGI 51 85115 119 ball B...

Page 27: ...OLD PROTRUSION END FLASH SHALL NOT EXCEED 0 0098 in 0 25 mm PER SIDE 3 DIMENSIONS IN MILLIMETERS BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 0 30 0 08 0 65 20 00 0 10 22 0...

Page 28: ...CY7C1386DV25 CY7C1386FV25 CY7C1387DV25 CY7C1387FV25 Document Number 38 05548 Rev E Page 28 of 30 Figure 2 119 Ball BGA 14 x 22 x 2 4 mm 51 85115 Package Diagrams continued 51 85115 B Feedback...

Page 29: ...s of Intel Corporation PowerPC is a trademark of IBM Corporation All product and company names mentioned in this document are the trademarks of their respective holders Figure 3 165 Ball FBGA 13 x 15...

Page 30: ...and 4 08 C W respectively Changed JA and JC for BGA Package from 45 and 7 C W to 23 8 and 6 2 C W respectively Changed JA and JC for FBGA Package from 46 and 3 C W to 20 7 and 4 0 C W respectively Mo...

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