Cypress Semiconductor CY7C1381D Specification Sheet Download Page 7

Page: 7 / 29

CY7C1381D, CY7C1381F

CY7C1383D, CY7C1383F

Document #: 38-05544 Rev. *F

Page 7 of 29

Functional Overview

All synchronous inputs pass through input registers controlled
by the rising edge of the clock. Maximum access delay from
the clock rise (t

CDV

) is 6.5 ns (133 MHz device).

The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F
supports secondary cache in systems utilizing a linear or
interleaved burst sequence. The interleaved burst order
supports Pentium

and i486™ processors. The linear burst

sequence is suited for processors that utilize a linear burst
sequence. The burst order is user selectable, and is
determined by sampling the MODE input. Accesses can be
initiated with the processor address strobe (ADSP) or the
controller address strobe (ADSC). Address advancement
through the burst sequence is controlled by the ADV input. A
two-bit on-chip wraparound burst counter captures the first
address in a burst sequence and automatically increments the
address for the rest of the burst access.
Byte write operations are qualified with the byte write enable
(BW

) and byte write select (BW

) inputs. A global write

enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed write circuitry.
Three synchronous chip selects (CE

, CE

[2]

) and an

asynchronous output enable (OE) provide for easy bank

selection and output tri-state control. ADSP is ignored if CE

is HIGH.

Single Read Accesses

A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE

, CE

, and CE

[2]

are all

asserted active, and (2) ADSP or ADSC is asserted LOW (if
the access is initiated by ADSC, the write inputs must be
deasserted during this first cycle). The address presented to
the address inputs is latched into the address register and the
burst counter and/or control logic, and later presented to the
memory core. If the OE input is asserted LOW, the requested
data will be available at the data outputs with a maximum to
t

CDV

after clock rise. ADSP is ignored if CE

is HIGH.

Single Write Accesses Initiated by ADSP

This access is initiated when the following conditions are
satisfied at clock rise: (1) CE

, CE

[2]

are all asserted

active, and (2) ADSP is asserted LOW. The addresses
presented are loaded into the address register and the burst
inputs (GW, BW

, and BW

) are ignored during this first clock

cycle. If the write inputs are asserted active (see

Truth Table

for Read/Write

[4, 9]

on page 10

for appropriate states that

indicate a write) on the next clock rise, the appropriate data will
be latched and written into the device. Byte writes are allowed.
All IOs are tri-stated during a byte write. As this is a common
IO device, the asynchronous OE input signal must be

MODE

Input-Static

Selects burst order

. When tied to GND selects linear burst sequence. When tied to V

or left floating selects interleaved burst sequence. This is a strap pin and must remain static
during device operation. Mode pin has an internal pull up.

Power Supply

Power supply inputs to the core of the device

DDQ

IO Power Supply

Power supply for the IO circuitry

Ground

Ground for the core of the device

SSQ

IO Ground

Ground for the IO circuitry

TDO

JTAG serial output