Cypress Semiconductor CY7C1365C Specification Sheet Download Page 13

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CY7C1365C

Document #: 38-05690 Rev. *E

Page 13 of 18

Timing Diagrams

Read Cycle Timing

[17]

Note:

17. On this diagram, when CE is LOW, CE

is LOW, CE

is HIGH and CE

is LOW. When CE is HIGH, CE

is HIGH or CE

is LOW or CE

is HIGH.

tCYC

CLK

tADH

tADS

ADDRESS

tAH

tAS

tCEH

tCES

Data Out (Q)

High-Z

tCLZ

tDOH

tCDV

tOEHZ

tCDV

Single READ

BURST

READ

tOEV

tOELZ

tCHZ

Burst wraps around
to its initial state

ADVH

ADVS

WEH

WES

tADH

tADS

Q(A2)

Q(A2 + 1)

Q(A2 + 2)

Q(A1)

Q(A2)

Q(A2 + 1)

Q(A2 + 2)

Q(A2 + 3)

ADV suspends burst.

Deselect Cycle

DON’T CARE

UNDEFINED

ADSP

ADSC

GW, BWE,BW

[A:D]

ADV

[+] Feedback

Summary of Contents for CY7C1365C

Page 1: ...ts include all addresses all data inputs address pipelining Chip Enable CE1 depth expansion Chip Enables CE2 and CE3 2 Burst Control inputs ADSC ADSP and ADV Write Enables BW A D and BWE and Global Wr...

Page 2: ...ARRAY MODE A 1 0 ZZ DQs A0 A1 A ADV CLK ADSP ADSC BWD BWC BWB BWA BWE CE1 CE2 CE3 OE GW SLEEP CONTROL DQA BYTE WRITE REGISTER DQB BYTE WRITE REGISTER DQC BYTE WRITE REGISTER BYTE WRITE REGISTER DQD BY...

Page 3: ...DDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD NC A A CE 1 CE 2 BWS D BWS C BWS B BWS A A V DD V SS CLK GW BWE OE ADSP A A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1...

Page 4: ...VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD NC A A CE 1 CE 2 BWS D BWS C BWS B BWS A CE 3 V DD V SS CLK GW BWE OE ADSP A A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17...

Page 5: ...throughout this document for BGA CE3 is sampled only when a new external address is loaded OE 86 Input Asynchronous Output Enable asynchronous input active LOW Controls the direction of the I O pins...

Page 6: ...60 71 76 I O Ground Ground for the I O circuitry MODE 31 Input Static Selects Burst Order When tied to GND selects linear burst sequence When tied to VDD or left floating selects interleaved burst seq...

Page 7: ...te writes BWA controls DQA and BWB controls DQB BWC controls DQC and BWD controls DQD All I Os are tri stated during a byte write Since this is a common I O device the asynchronous OE input signal mus...

Page 8: ...Burst Next H X X L X H L H L L H Q Read Cycle Continue Burst Next H X X L X H L H H L H Tri State Write Cycle Continue Burst Next X X X L H H L L X L H D Write Cycle Continue Burst Next H X X L X H L...

Page 9: ...H H Write Bytes C A DQPC DQPA H L H L H L Write Bytes C B DQPC DQPB H L H L L H Write Bytes C B A DQPC DQPB DQPA H L H L L L Write Byte D DQPD H L L H H H Write Bytes D A DQPD DQPA H L L H H L Write B...

Page 10: ...IH Input HIGH Voltage for 3 3V I O 2 0 VDD 0 3V V for 2 5V I O 1 7 VDD 0 3V V VIL Input LOW Voltage 8 for 3 3V I O 0 3 0 8 V for 2 5V I O 0 3 0 7 V IX Input Leakage Current except ZZ and MODE GND VI V...

Page 11: ...ollow standard test methods and procedures for measuring thermal impedance per EIA JESD51 29 41 C W JC Thermal Resistance Junction to Case 6 13 C W AC Test Loads and Waveforms OUTPUT R 317 R 351 5 pF...

Page 12: ...s tADH ADSP ADSC Hold after CLK Rise 0 5 0 5 ns tWEH GW BWE BW A D Hold after CLK Rise 0 5 0 5 ns tADVH ADV Hold after CLK Rise 0 5 0 5 ns tDH Data Input Hold after CLK Rise 0 5 0 5 ns tCEH Chip Enabl...

Page 13: ...CE2 is LOW or CE3 is HIGH tCYC tCL CLK tADH tADS ADDRESS t CH tAH tAS A1 tCEH tCES Data Out Q High Z tCLZ tDOH tCDV tOEHZ tCDV Single READ BURST READ tOEV tOELZ tCHZ Burst wraps around to its initial...

Page 14: ...iming Diagrams continued tCYC t CL CLK tADH tADS ADDRESS t CH tAH tAS A1 tCEH tCES High Z BURST READ BURST WRITE D A2 D A2 1 D A2 1 D A1 D A3 D A3 1 D A3 2 D A2 3 A2 A3 Extended BURST WRITE D A2 2 Sin...

Page 15: ...ed tCYC t CL CLK tADH tADS ADDRESS t CH tAH tAS A2 tCEH tCES Single WRITE D A3 A3 A4 BURST READ Back to Back READs High Z Q A2 Q A4 Q A4 1 Q A4 2 Q A4 3 t WEH t WES t OEHZ tDH tDS tCDV tOELZ A1 A5 A6...

Page 16: ...ial CY7C1365C 133AJXI 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free 2 Chip Enable 100 CY7C1365C 100AXC 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free 3 Chip Enable Commercial...

Page 17: ...press products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Intel and Pentium are registered t...

Page 18: ...page 6 Added Industrial operating range Updated Ordering Information Table B 377095 See ECN PCI Changed ISB2 from 30 to 40 mA Modified test condition in note 9 from VIH VDD to VIH VDD C 408725 See EC...

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