Cypress Semiconductor CY7C1364C Specification Sheet Download Page 16

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CY7C1364C

Document #: 38-05689 Rev. *E

Page 16 of 18

Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

visit

www.cypress.com

for actual products offered.

Speed

(MHz)

Ordering Code

Package
Diagram

Part and Package Type

Operating

Range

166

CY7C1364C-166AXC

51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

(3 Chip Enable)

Commercial

CY7C1364C-166AJXC

100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(2 Chip Enable)

CY7C1364C-166AXI

100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(3 Chip Enable)

Industrial

CY7C1364C-166AJXI

100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(2 Chip Enable)

200

CY7C1364C-200AXC

51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

(3 Chip Enable)

Commercial

CY7C1364C-200AJXC

100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(2 Chip Enable)

CY7C1364C-200AXI

100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(3 Chip Enable)

Industrial

CY7C1364C-200AJXI

100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(2 Chip Enable)

250

CY7C1364C-250AXC

51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

(3 Chip Enable)

Commercial

CY7C1364C-250AJXC

100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(2 Chip Enable)

CY7C1364C-250AXI

100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(3 Chip Enable)

Industrial

CY7C1364C-250AJXI

100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
(2 Chip Enable)

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Summary of Contents for CY7C1364C

Page 1: ...inputs include the Output Enable OE and the ZZ pin Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor ADSP or Address Strobe Controller ADSC are ac...

Page 2: ...QA NC NC DQC DQC VDDQ VSSQ DQC DQC DQC DQC VSSQ VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD NC A A CE 1 CE 2 BW D BW C BW B BW A A V DD V SS CLK GW BWE OE ADSC ADSP...

Page 3: ...DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD NC A A CE 1 CE 2 BW D BW C BW B BW A CE 3 V DD V SS CLK GW BWE OE ADSC ADSP ADV A A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 2...

Page 4: ...hen a new external address is loaded OE 86 Input Asynchronous Output Enable asynchronous input active LOW Controls the direction of the I O pins When LOW the I O pins behave as outputs When deasserted...

Page 5: ...ress advancement logic while being delivered to the RAM array The Write signals GW BWE and BW A D and ADV inputs are ignored during this first cycle ADSP triggered Write accesses require two clock cyc...

Page 6: ...egrity is guaranteed Accesses pending when entering the sleep mode are not considered valid nor is the completion of the operation guaranteed The device must be deselected prior to entering the sleep...

Page 7: ...ri State Write Continue Write Next L X X H X H H X Tri State Write Suspend Write Current L X X X H H H X Tri State Write Suspend Write Current L X X H X H H X Tri State Write ZZ Sleep None H X X X X X...

Page 8: ...e Bytes B A H L H H L L Write Byte C DQC H L H L H H Write Bytes C A H L H L H L Write Bytes C B H L H L L H Write Bytes C B A H L H L L L Write Byte D DQD H L L H H H Write Bytes D A H L L H H L Writ...

Page 9: ...V for 2 5V I O 1 7 VDD 0 3V V VIL Input LOW Voltage 9 for 3 3 V I O 0 3 0 8 V for 2 5V I O 0 3 0 7 V IX Input Leakage Current except ZZ and MODE GND VI VDDQ 5 5 A Input Current of MODE Input VSS 30 A...

Page 10: ...ollow standard test methods and procedures for measuring thermal impedance per EIA JESD51 29 41 C W JC Thermal Resistance Junction to Case 6 13 C W AC Test Loads and Waveforms Note 11 Tested initially...

Page 11: ...ld Times tAH Address Hold after CLK Rise 0 4 0 5 0 5 ns tADH ADSP ADSC Hold after CLK Rise 0 4 0 5 0 5 ns tADVH ADV Hold after CLK Rise 0 4 0 5 0 5 ns tWEH GW BWE BW A D Hold after CLK Rise 0 4 0 5 0...

Page 12: ...HIGH or CE2 is LOW or CE3 is HIGH tCYC t CL CLK ADSP t ADH t ADS ADDRESS t CH OE ADSC CE tAH tAS A1 tCEH tCES GW BWE BW A D Data Out Q High Z tCLZ tDOH tCO ADV tOEHZ tCO tOEV tOELZ tCHZ ADV suspends...

Page 13: ...ADS ADDRESS tCH OE ADSC CE tAH tAS A1 tCEH tCES BWE BW A D Data Out Q High Z ADV BURST READ BURST WRITE D A2 D A2 1 D A2 1 D A1 D A3 D A3 1 D A3 2 D A2 3 A2 A3 Data In D Extended BURST WRITE D A2 2 Si...

Page 14: ...e is performed 21 GW is HIGH Switching Waveforms continued tCYC tCL CLK ADSP tADH tADS ADDRESS tCH OE ADSC CE tAH tAS A2 tCEH tCES BWE BW A D Data Out Q High Z ADV Single WRITE D A3 A4 A5 A6 D A5 D A6...

Page 15: ...entering ZZ mode See Cycle Descriptions table for all possible signal conditions to deselect the device 23 DQs are in High Z when exiting ZZ sleep mode Switching Waveforms continued t ZZ I SUPPLY CLK...

Page 16: ...Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free 2 Chip Enable 200 CY7C1364C 200AXC 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free 3 Chip Enable Commercial CY7C1364C 200AJXC 100 pin Th...

Page 17: ...upport systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges i486 is a trademark and Intel and Pentium are registered t...

Page 18: ...ion Updated Ordering Information Table B 377095 See ECN PCI Changed ISB2 from 30 to 40 mA Modified test condition in note 9 from VIH VDD to VIH VDD C 408725 See ECN RXU Changed address of Cypress Semi...

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