Cypress Semiconductor CY7C1353G, Specification Sheet

Page: 9 / 13

CY7C1353G
Document #: 38-05515 Rev. *E Page 9 of 13
Switching Characteristics
Over the Operating Range
[17, 18]
Parameter Description
–133 –100
Unit Min Max Min Max
t
POWER
V
DD
(Typical) to the first Access
[13]
1 1 ms
Clock
t
CYC
Clock Cycle Time 7.5 10 ns
t
CH
Clock HIGH 2.5 4.0 ns
t
CL
Clock LOW 2.5 4.0 ns
Output Times
t
CDV
Data Output Valid After CLK Rise 6.5 8.0 ns
t
DOH
Data Output Hold After CLK Rise 2.0 2.0 ns
t
CLZ
Clock to Low-Z
[14, 15, 16]
0 0 ns
t
CHZ
Clock to High-Z
[14, 15, 16]
3.5 3.5 ns
t
OEV
OE LOW to Output Valid 3.5 3.5 ns
t
OELZ
OE LOW to Output Low-Z
[14, 15, 16]
0 0 ns
t
OEHZ
OE HIGH to Output High-Z
[14, 15, 16]
3.5 3.5 ns
Setup Times
t
AS
Address Setup Before CLK Rise 1.5 2.0 ns
t
ALS
ADV/LD Setup Before CLK Rise 1.5 2.0 ns
t
WES
WE, BW
X
Setup Before CLK Rise 1.5 2.0 ns
t
CENS
CEN Setup Before CLK Rise 1.5 2.0 ns
t
DS
Data Input Setup Before CLK Rise 1.5 2.0 ns
t
CES
Chip Enable Setup Before CLK Rise 1.5 2.0 ns
Hold Times
t
AH
Address Hold After CLK Rise 0.5 0.5 ns
t
ALH
ADV/LD Hold after CLK Rise 0.5 0.5 ns
t
WEH
WE, BW
X
Hold After CLK Rise 0.5 0.5 ns
t
CENH
CEN Hold After CLK Rise 0.5 0.5 ns
t
DH
Data Input Hold After CLK Rise 0.5 0.5 ns
t
CEH
Chip Enable Hold After CLK Rise 0.5 0.5 ns
Notes:
13.This part has a voltage regulator internally; t
POWER
is the time that the power needs to be supplied above V
DD
minimum initially before a read or write operation
can be initiated.
14.t
CHZ
, t
CLZ
,t
OELZ
, and t
OEHZ
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
15.At any voltage and temperature, t
OEHZ
is less than t
OELZ
and t
CHZ
is less than t
CLZ
to eliminate bus contention between SRAMs when sharing the same data
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to
achieve tri-state prior to Low-Z under the same system conditions.
16.This parameter is sampled and not 100% tested.
17.Timing reference level is 1.5V when V
DDQ
=3.3V and is 1.25V when V
DDQ
=2.5V.
18.Test conditions shown in (a) of AC Test Loads, unless otherwise noted.
[+] Feedback