Cypress Semiconductor CY7C1353G Specification Sheet Download Page 2

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CY7C1353G

Document #: 38-05515 Rev. *E

Page 2 of 13

Selection Guide

133 MHz

100 MHz

Unit

Maximum Access Time

6.5

8.0

Maximum Operating Current

225

205

Maximum CMOS Standby Current

Pin Configuration

100-Pin TQFP Pinout

NC/28

NC/

NC/36M

A
NC
NC
V

DDQ

NC
DQP

DDQ

NC
V

DDQ

NC
NC
V

DDQ

NC
NC
NC

DDQ

NC
NC

DDQ

DQP

DDQ

NC
NC
NC

CLK

CEN

NC/18M

1
2
3
4
5
6
7
8
9

11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58

57
56
55
54
53
52
51

NC/9M

ADV

/LD

MODE

NC/72M

CY7C1353G

BYTE A

BYTE B

[+] Feedback

Summary of Contents for CY7C1353G

Page 1: ... every clock cycle This feature dramatically improves the throughput of data through the SRAM especially in systems that require frequent Write Read transitions All synchronous inputs pass through input registers controlled by the rising edge of the clock The clock input is qualified by the Clock Enable CEN signal which when deasserted suspends operation and extends the previous clock cycle Maximu...

Page 2: ...A DQA NC NC VSS VDDQ NC NC NC NC NC NC VDDQ VSS NC NC DQB DQB VSS VDDQ DQB DQB NC VDD NC VSS DQB DQB VDDQ VSS DQB DQB DQPB NC VSS VDDQ NC NC NC A A CE 1 CE 2 NC NC BW B BW A CE 3 V DD V SS CLK WE CEN OE NC 18M A A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 ...

Page 3: ... of a write sequence during the first clock when emerging from a deselected state when the device has been deselected CEN Input Synchronous Clock Enable Input Active LOW When asserted LOW the Clock signal is recognized by the SRAM When deasserted HIGH the Clock signal is masked While deasserting CEN does not deselect the device CEN can be used to extend the previous cycle when required ZZ Input As...

Page 4: ...ed sufficiently A HIGH input on ADV LD increments the internal burst counter regardless of the state of chip enable inputs or WE WE is latched at the beginning of a burst cycle Therefore the type of access Read or Write is maintained throughout the burst sequence Single Write Accesses Write access are initiated when these conditions are satisfied at clock rise CEN is asserted LOW CE1 CE2 and CE3 a...

Page 5: ... X X X L H X X L L L H Data Out Q NOP DUMMY READ Begin Burst External L H L L L H X H L L H Tri State DUMMY READ Continue Burst Next X X X L H X X H L L H Tri State WRITE Cycle Begin Burst External L H L L L L L X L L H Data In D WRITE Cycle Continue Burst Next X X X L H X L X L L H Data In D NOP WRITE ABORT Begin Burst None L H L L L L H X L L H Tri State WRITE ABORT Continue Burst Next X X X L H...

Page 6: ... BWB Read H X X Write No bytes written L H H Write Byte A DQA and DQPA L L H Write Byte B DQB and DQPB L H L Write All Bytes L L L Note 9 Table only lists a partial listing of the byte write combinations Any combination of BW A D is valid Appropriate write is based on which byte write is active Feedback ...

Page 7: ... 5V IO 1 7 VDD 0 3V V VIL Input LOW Voltage 10 for 3 3V IO 0 3 0 8 V Input LOW Voltage 10 for 2 5V IO 0 3 0 7 V IX Input Leakage Current except ZZ and MODE GND VI VDDQ 5 5 µA Input Current of MODE Input VSS 30 µA Input VDD 5 µA Input Current of ZZ Input VSS 5 µA Input VDD 30 µA IOZ Output Leakage Current GND VI VDDQ Output Disabled 5 5 µA IDD VDD Operating Supply Current VDD Max IOUT 0 mA f fMAX 1...

Page 8: ...ndard test methods and procedures for measuring thermal impedance according to EIA JESD51 30 32 C W ΘJC Thermal Resistance Junction to Case 6 85 C W AC Test Loads and Waveforms Note 12 Tested initially and after any design or process changes that may affect these parameters OUTPUT R 317Ω R 351Ω 5 pF INCLUDING JIG AND SCOPE a b OUTPUT RL 50Ω Z0 50Ω VT 1 5V 3 3V ALL INPUT PULSES VDDQ GND 90 10 90 10...

Page 9: ...5 0 5 ns tALH ADV LD Hold after CLK Rise 0 5 0 5 ns tWEH WE BWX Hold After CLK Rise 0 5 0 5 ns tCENH CEN Hold After CLK Rise 0 5 0 5 ns tDH Data Input Hold After CLK Rise 0 5 0 5 ns tCEH Chip Enable Hold After CLK Rise 0 5 0 5 ns Notes 13 This part has a voltage regulator internally tPOWER is the time that the power needs to be supplied above VDD minimum initially before a read or write operation ...

Page 10: ...ence is determined by the status of the MODE 0 Linear 1 Interleaved Burst operations are optional WRITE D A1 1 2 3 4 5 6 7 8 9 CLK tCYC tCL tCH 10 CE tCEH tCES WE CEN tCENH tCENS BW A B ADV LD tAH tAS ADDRESS A1 A2 A3 A4 A5 A6 A7 tDH tDS DQ COMMAND tCLZ D A1 D A2 Q A4 Q A3 D A2 1 tDOH tCHZ tCDV WRITE D A2 BURST WRITE D A2 1 READ Q A3 READ Q A4 BURST READ Q A4 1 WRITE D A5 READ Q A6 WRITE D A7 DESE...

Page 11: ... See truth table for all possible signal conditions to deselect the device 24 DQs are in high Z when exiting ZZ sleep mode Switching Waveforms READ Q A3 4 5 6 7 8 9 10 A3 A4 A5 D A4 1 2 3 CLK CE WE CEN BW A B ADV LD ADDRESS DQ COMMAND WRITE D A4 STALL WRITE D A1 READ Q A2 STALL NOP READ Q A5 DESELECT CONTINUE DESELECT DON T CARE UNDEFINED tCHZ A1 A2 Q A2 D A1 Q A3 tDOH Q A5 tZZ I SUPPLY CLK ZZ tZZ...

Page 12: ...press Semiconductor All product and company names mentioned in this document are the trademarks of their respective holders Ordering Information Not all of the speed package and temperature ranges are available Please contact your local sales representative or visit www cypress com for actual products offered Speed MHz Ordering Code Package Diagram Part and Package Type Operating Range 133 CY7C135...

Page 13: ...values on the Thermal Resistance table Updated the Ordering Information by shading and unshading MPNs according to availability C 418633 See ECN RXU Converted from Preliminary to Final Changed address of Cypress Semiconductor Corporation on Page 1 from 3901 North First Street to 198 Champion Court Modified test condition from VIH VDD to VIH VDD Modified test condition from VDDQ VDD to VDDQ VDD Mod...

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