Cypress Semiconductor CY7C1346H Specification Sheet Download Page 11

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CY7C1346H

Document #: 38-05672 Rev. *B

Page 11 of 16

Switching Waveforms

Read Cycle Timing

[17]

Note:

17. On this diagram, when CE is LOW, CE

is LOW, CE

is HIGH and CE

is LOW. When CE is HIGH, CE

is HIGH or CE

is LOW or CE

is HIGH.

tCYC

CLK

ADSP

ADH

ADS

ADDRESS

ADSC

tAH

tAS

tCEH

tCES

GW, BWE,

[A:D]

Data Out (Q)

High-Z

tCLZ

tDOH

tCO

ADV

tOEHZ

tCO

Single READ

BURST READ

tOEV

tOELZ

tCHZ

ADV
suspends
burst.

Burst wraps around
to its initial state

tADVH

tADVS

tWEH

tWES

tADH

tADS

Q(A2)

Q(A2 + 1)

Q(A2 + 2)

Q(A1)

Q(A2)

Q(A2 + 1)

Q(A2 + 3)

Deselect
cycle

Burst continued with
new base address

DON’T CARE

UNDEFINED

[+] Feedback

Summary of Contents for CY7C1346H

Page 1: ...le OE and the ZZ pin Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor ADSP or Address Strobe Controller ADSC are active Subsequent burst addresses...

Page 2: ...QA DQPA DQPc DQc DQC VDDQ VSSQ DQC DQC DQC DQC VSSQ VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD DQPD A A CE 1 CE 2 BW D BW C BW B BW A CE 3 V DD V SS CLK GW BWE OE A...

Page 3: ...put Asynchronous Output Enable asynchronous input active LOW Controls the direction of the I O pins When LOW the I O pins behave as outputs When deasserted HIGH I O pins are tri stated and act as inpu...

Page 4: ...ncement logic while being delivered to the RAM array The Write signals GW BWE and BW A D and ADV inputs are ignored during this first cycle ADSP triggered Write accesses require two clock cycles to co...

Page 5: ...egrity is guaranteed Accesses pending when entering the sleep mode are not considered valid nor is the completion of the operation guaranteed The device must be deselected prior to entering the sleep...

Page 6: ...ycle Continue Burst Next H X X L X H L L X L H D READ Cycle Suspend Burst Current X X X L H H H H L L H Q READ Cycle Suspend Burst Current X X X L H H H H H L H Tri State READ Cycle Suspend Burst Curr...

Page 7: ...H X X X X Read H L H H H H Write Byte A DQA and DQPA H L H H H L Write Byte B DQB and DQPB H L H H L H Write Bytes B A H L H H L L Write Byte C DQC and DQPC H L H L H H Write Bytes C A H L H L H L Wri...

Page 8: ...for 3 3V I O IOL 8 0 mA 0 4 V for 2 5V I O IOL 1 0 mA 0 4 VIH Input HIGH Voltage 8 for 3 3V I O 2 0 VDD 0 3V V for 2 5V I O 1 7 VDD 0 3V V VIL Input LOW Voltage 8 for 3 3V I O 0 3 0 8 V for 2 5V I O 0...

Page 9: ...ollow standard test methods and procedures for measuring thermal impedance per EIA JESD51 30 32 C W JC Thermal Resistance Junction to Case 6 85 C W AC Test Loads and Waveforms Note 10 Tested initially...

Page 10: ...ld after CLK Rise 0 5 ns tADVH ADV Hold after CLK Rise 0 5 ns tWEH GW BWE BW A D Hold after CLK Rise 0 5 ns tDH Data Input Hold after CLK Rise 0 5 ns tCEH Chip Enable Hold after CLK Rise 0 5 ns Notes...

Page 11: ...CE3 is HIGH tCYC t CL CLK ADSP t ADH t ADS ADDRESS t CH OE ADSC CE tAH tAS A1 tCEH tCES GW BWE BW A D Data Out Q High Z tCLZ tDOH tCO ADV tOEHZ tCO Single READ BURST READ tOEV tOELZ tCHZ ADV suspends...

Page 12: ...ADS ADDRESS tCH OE ADSC CE tAH tAS A1 tCEH tCES BWE BW A D Data Out Q High Z ADV BURST READ BURST WRITE D A2 D A2 1 D A2 1 D A1 D A3 D A3 1 D A3 2 D A2 3 A2 A3 Data In D Extended BURST WRITE D A2 2 Si...

Page 13: ...e is performed 20 GW is HIGH Switching Waveforms continued tCYC tCL CLK ADSP tADH tADS ADDRESS tCH OE ADSC CE tAH tAS A2 tCEH tCES BWE BW A D Data Out Q High Z ADV Single WRITE D A3 A4 A5 A6 D A5 D A6...

Page 14: ...entering ZZ mode See Cycle Descriptions table for all possible signal conditions to deselect the device 22 DQs are in High Z when exiting ZZ sleep mode Switching Waveforms continued t ZZ I SUPPLY CLK...

Page 15: ...oration PowerPC is a registered trademark of IBM Corporation All product and company names mentioned in this document may be trademarks of their respective holders Ordering Information Not all of the...

Page 16: ...ress Semiconductor Corporation on Page 1 from 3901 North First Street to 198 Champion Court Removed 133MHz Speed bin Changed three state to tri state Modified test condition from VIH VDD to VIH VDD Mo...

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