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PRELIMINARY

CY7C1336H

Document #: 001-00210 Rev. *A

Page 15 of 15

Document History Page

Document Title: CY7C1336H 2-Mbit (64K x 32) Flow-Through Sync SRAM
Document Number: 001-00210

REV.

ECN NO.

Issue Date

Orig. of 

Change

Description of Change

**

347377

See ECN

PCI

New Data Sheet

*A

428408

See ECN

NXR

Changed address of Cypress Semiconductor Corporation on Page# 1 from 
“3901 North First Street” to “198 Champion Court”
Changed Three-State to Tri-State.
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the 
Electrical Characteristics Table.
Modified test condition from V

IH

 < V

DD 

to

 

V

IH 

V

DD

Replaced Package Name column with Package Diagram in the Ordering 
Information table.
Replaced Package Diagram of 51-85050 from *A to *B

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Summary of Contents for CY7C1336H

Page 1: ...ADSP and ADV Write Enables BW A D and BWE and Global Write GW Asynchronous inputs include the Output Enable OE and the ZZ pin The CY7C1336H allows either interleaved or linear burst sequences selecte...

Page 2: ...DQA VSSQ VDDQ DQA DQA NC NC DQC DQC VDDQ VSSQ DQC DQC DQC DQC VSSQ VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD NC A A CE1 CE 2 BW D BW C BW B BW A CE 3 V DD V SS CL...

Page 3: ...merging from a deselected state ADV Input Synchronous Advance Input signal sampled on the rising edge of CLK When asserted it automatically incre ments the address in a burst cycle ADSP Input Synchron...

Page 4: ...ing Byte Writes BWA controls DQA and BWB controls DQB BWC controls DQC and BWD controls DQD All I Os are tri stated during a Byte Write Since this is a common I O device the asynchronous OE input sign...

Page 5: ...ontinue Burst Next H X X L X H L H L L H Q Read Cycle Continue Burst Next H X X L X H L H H L H Tri State Write Cycle Continue Burst Next X X X L H H L L X L H D Write Cycle Continue Burst Next H X X...

Page 6: ...L H L H H Write Bytes C A DQPC DQPA H L H L H L Write Bytes C B DQPC DQPB H L H L L H Write Bytes C B A DQPC DQPB DQPA H L H L L L Write Byte D DQPD H L L H H H Write Bytes D A DQPD DQPA H L L H H L W...

Page 7: ...0 3 0 8 V IX Input Leakage Current except ZZ and MODE GND VI VDDQ 5 5 A Input Current of MODE Input VSS 30 A Input VDD 5 A Input Current of ZZ Input VSS 5 A Input VDD 30 A IOZ Output Leakage Current G...

Page 8: ...ns 100 TQFP Package Unit JA Thermal Resistance Junction to Ambient Test conditions follow standard test methods and procedures for measuring thermal impedance per EIA JESD51 30 32 C W JC Thermal Resis...

Page 9: ...after CLK Rise 0 5 0 5 ns tADH ADSP ADSC Hold after CLK Rise 0 5 0 5 ns tWEH GW BWE BW A D Hold after CLK Rise 0 5 0 5 ns tADVH ADV Hold after CLK Rise 0 5 0 5 ns tDH Data Input Hold after CLK Rise 0...

Page 10: ...IGH or CE2 is LOW or CE3 is HIGH tCYC tCL CLK tADH tADS ADDRESS t CH tAH tAS A1 tCEH tCES Data Out Q High Z tCLZ tDOH tCDV tOEHZ tCDV Single READ BURST READ tOEV tOELZ tCHZ Burst wraps around to its i...

Page 11: ...S ADDRESS t CH tAH tAS A1 tCEH tCES High Z BURST READ BURST WRITE D A2 D A2 1 D A2 1 D A1 D A3 D A3 1 D A3 2 D A2 3 A2 A3 Extended BURST WRITE D A2 2 Single WRITE tADH tADS tADH tADS t OEHZ tADVH tADV...

Page 12: ...ADV cycle is performed 19 GW is HIGH Timing Diagrams continued tCYC t CL CLK tADH tADS ADDRESS t CH tAH tAS A2 tCEH tCES Single WRITE D A3 A3 A4 BURST READ Back to Back READs High Z Q A2 Q A4 Q A4 1 Q...

Page 13: ...ed when entering ZZ mode See Cycle Descriptions table for all possible signal conditions to deselect the device 21 DQs are in High Z when exiting ZZ sleep mode Timing Diagrams continued t ZZ I SUPPLY...

Page 14: ...any names mentioned in this document may be the trademarks of their respective holders Ordering Information Speed MHz Ordering Code Package Diagram Package Type Operating Range 133 CY7C1336H 133AXC 51...

Page 15: ...t A 428408 See ECN NXR Changed address of Cypress Semiconductor Corporation on Page 1 from 3901 North First Street to 198 Champion Court Changed Three State to Tri State Modified Input Load to Input L...

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