Cypress Semiconductor CY7C1297H Specification Sheet Download Page 14

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CY7C1297H

Document #: 38-05669 Rev. *B

Page 14 of 15

© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

visit

www.cypress.com

for actual products offered.

Speed

(MHz)

Ordering Code

Package
Diagram

Package Type

Operating

Range

100

CY7C1297H-100AXC

51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

Commercial

CY7C1297H-100AXI

Industrial

133

CY7C1297H-133AXC

51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

Commercial

CY7C1297H-133AXI

Industrial

Package Diagram

NOTE:

1. JEDEC STD REF MS-026

2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH

MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE

3. DIMENSIONS IN MILLIMETERS

BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH

0.30±0.08

0.65

20.00±0.10

22.00±0.20

1.40±0.05

12°±1°

1.60 MAX.

0.05 MIN.

0.60±0.15

0° MIN.

0.25

0°-7°

(8X)

STAND-OFF

R 0.08 MIN.

TYP.

0.20 MAX.

0.15 MAX.

0.20 MAX.

R 0.08 MIN.

0.20 MAX.

14.00±0.10

16.00±0.20

0.10

SEE DETAIL

DETAIL

100

GAUGE PLANE

1.00 REF.

0.20 MIN.

SEATING PLANE

100-Pin TQFP (14 x 20 x 1.4 mm) (51-85050)

51-85050-*B

[+] Feedback

Summary of Contents for CY7C1297H

Page 1: ...and CE3 Burst Control inputs ADSC ADSP and ADV Write Enables BW A B and BWE and Global Write GW Asynchronous inputs include the Output Enable OE and the ZZ pin The CY7C1297H allows either interleaved or linear burst sequences selected by the MODE input pin A HIGH selects an interleaved burst sequence while a LOW selects a linear burst sequence Burst accesses can be initiated with the Processor Add...

Page 2: ...NC NC VSS VDDQ NC NC NC NC NC NC VDDQ VSS NC NC DQB DQB VSS VDDQ DQB DQB NC VDD NC VSS DQB DQB VDDQ VSS DQB DQB DQPB NC VSS VDDQ NC NC NC A A CE 1 CE 2 NC NC BW B BW A CE 3 V DD V SS CLK GW BWE OE ADSP A A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63...

Page 3: ...e when emerging from a deselected state ADV Input Synchronous Advance Input signal sampled on the rising edge of CLK When asserted it automatically increments the address in a burst cycle ADSP Input Synchronous Address Strobe from Processor sampled on the rising edge of CLK active LOW When asserted LOW addresses presented to the device are captured in the address registers A 1 0 are also loaded in...

Page 4: ... device Byte Writes are allowed During byte writes BWA controls DQA and BWB controls DQB All I Os are tri stated during a Byte Write Since this is a common I O device the asynchronous OE input signal must be deasserted and the I Os must be tri stated prior to the presentation of data to DQs As a safety precaution the data lines are tri stated once a Write cycle is detected regardless of the state ...

Page 5: ... Continue Burst Next H X X L X H L H L L H Q Read Cycle Continue Burst Next H X X L X H L H H L H Tri State Write Cycle Continue Burst Next X X X L H H L L X L H D Write Cycle Continue Burst Next H X X L X H L L X L H D Read Cycle Suspend Burst Current X X X L H H H H L L H Q Read Cycle Suspend Burst Current X X X L H H H H H L H Tri State Read Cycle Suspend Burst Current H X X L X H H H L L H Q R...

Page 6: ...t 38 05669 Rev B Page 6 of 15 Truth Table for Read Write 2 3 Function GW BWE BWB BWA Read H H X X Read H L H H Write Byte A DQPA H L H L Write Byte B DQPB H L L H Write All Bytes H L L L Write All Bytes L X X X Feedback ...

Page 7: ...V for 2 5V I O 1 7 VDD 0 3V V VIL Input LOW Voltage 7 for 3 3V I O 0 3 0 8 V for 2 5V I O 0 3 0 7 V IX Input Leakage Current except ZZ and MODE GND VI VDDQ 5 5 µA Input Current of MODE Input VSS 30 µA Input VDD 5 µA Input Current of ZZ Input VSS 5 µA Input VDD 30 µA IOZ Output Leakage Current GND VI VDDQ Output Disabled 5 5 µA IDD VDD Operating Supply Current VDD Max IOUT 0 mA f fMAX 1 tCYC 7 5 ns...

Page 8: ...w standard test methods and procedures for measuring thermal impedance per EIA JESD51 30 32 C W ΘJC Thermal Resistance Junction to Case 6 85 C W AC Test Loads and Waveforms Note 9 Tested initially and after any design or process change that may affect these parameters OUTPUT R 317Ω R 351Ω 5 pF INCLUDING JIG AND SCOPE a b OUTPUT RL 50Ω Z0 50Ω VT 1 5V 3 3V ALL INPUT PULSES VDDQ GND 90 10 90 10 1 ns ...

Page 9: ... 5 0 5 ns tADH ADSP ADSC Hold after CLK Rise 0 5 0 5 ns tWEH GW BWE BW A B Hold after CLK Rise 0 5 0 5 ns tADVH ADV Hold after CLK Rise 0 5 0 5 ns tDH Data Input Hold after CLK Rise 0 5 0 5 ns tCEH Chip Enable Hold after CLK Rise 0 5 0 5 ns Notes 10 Timing reference level is 1 5V when VDDQ 3 3V and is 1 25V when VDDQ 2 5V 11 Test conditions shown in a of AC Test Loads unless otherwise noted 12 Thi...

Page 10: ... CE2 is LOW or CE3 is HIGH tCYC tCL CLK tADH tADS ADDRESS t CH tAH tAS A1 tCEH tCES Data Out Q High Z tCLZ tDOH tCDV tOEHZ tCDV Single READ BURST READ tOEV tOELZ tCHZ Burst wraps around to its initial state t ADVH t ADVS t WEH t WES tADH tADS Q A2 Q A2 1 Q A2 2 Q A1 Q A2 Q A2 1 Q A2 2 Q A2 3 A2 ADV suspends burst Deselect Cycle DON T CARE UNDEFINED ADSP ADSC GW BWE BW A B CE ADV OE Feedback ...

Page 11: ...RESS t CH tAH tAS A1 tCEH tCES High Z BURST READ BURST WRITE D A2 D A2 1 D A2 1 D A1 D A3 D A3 1 D A3 2 D A2 3 A2 A3 Extended BURST WRITE D A2 2 Single WRITE tADH tADS tADH tADS t OEHZ tADVH tADVS tWEH tWES t DH t DS t WEH t WES Byte write signals are ignored for first cycle when ADSP initiates burst ADSC extends burst ADV suspends burst DON T CARE UNDEFINED ADSP ADSC BWE BW A B GW CE ADV OE Data ...

Page 12: ...ycle is performed 19 GW is HIGH Timing Diagrams continued tCYC t CL CLK tADH tADS ADDRESS t CH tAH tAS A2 tCEH tCES Single WRITE D A3 A3 A4 BURST READ Back to Back READs High Z Q A2 Q A4 Q A4 1 Q A4 2 Q A4 3 t WEH t WES t OEHZ tDH tDS tCDV tOELZ A1 A5 A6 D A5 D A6 Q A1 Back to Back WRITEs DON T CARE UNDEFINED ADSP ADSC BWE BW A B CE ADV OE Data In D Data Out Q Feedback ...

Page 13: ...hen entering ZZ mode See Cycle Descriptions table for all possible signal conditions to deselect the device 21 DQs are in High Z when exiting ZZ sleep mode Timing Diagrams continued tZZ I SUPPLY CLK ZZ tZZREC ALL INPUTS except ZZ DON T CARE I DDZZ tZZI tRZZI Outputs Q High Z DESELECT or READ Only Feedback ...

Page 14: ... all charges Ordering Information Not all of the speed package and temperature ranges are available Please contact your local sales representative or visit www cypress com for actual products offered Speed MHz Ordering Code Package Diagram Package Type Operating Range 100 CY7C1297H 100AXC 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Commercial CY7C1297H 100AXI Industrial 133 CY7...

Page 15: ...poration on Page 1 from 3901 North First Street to 198 Champion Court Added 2 5VI O option Changed Three State to Tri State Included Maximum Ratings for VDDQ relative to GND Modified Input Load to Input Leakage Current except ZZ and MODE in the Electrical Characteristics Table Modified test condition from VIH VDD to VIH VDD Replaced Package Name column with Package Diagram in the Ordering Informat...

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