Cypress Semiconductor CY7C1218H Specification Sheet Download Page 12

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CY7C1218H

Document #: 38-05667 Rev. *B

Page 12 of 16

Read/Write Cycle Timing

[17, 19, 20]

Notes:

19. The data bus (Q) remains in High-Z following a Write cycle unless an ADSP, ADSC, or ADV cycle is performed.
20. GW is HIGH.

Switching Waveforms

(continued)

tCYC

tCL

CLK

ADSP

tADH

tADS

ADDRESS

tCH

ADSC

tAH

tAS

tCEH

tCES

BWE,

BW[A:D]

Data Out (Q)

High-Z

ADV

Single WRITE

D(A3)

D(A5)

D(A6)

Data In (D)

BURST READ

Back-to-Back READs

High-Z

Q(A2)

Q(A1)

Q(A4)

Q(A4+1)

Q(A4+2)

tWEH

tWES

Q(A4+3)

tOEHZ

tDH

tDS

tOELZ

tCLZ

tCO

Back-to-Back

WRITEs

DON’T CARE

UNDEFINED

[+] Feedback

Summary of Contents for CY7C1218H

Page 1: ...ut Enable OE and the ZZ pin Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor ADSP or Address Strobe Controller ADSC are active Subsequent burst addresses can be internally generated as controlled by the Advance pin ADV Address data inputs and write controls are registered on chip to initiate a self timed Write cycle This part supports Byte Writ...

Page 2: ... VDDQ DQA DQA DQPA DQPC DQC DQC VDDQ VSSQ DQC DQC DQC DQC VSSQ VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD DQPD A A CE 1 CE 2 BW D BW C BW B BW A CE 3 V DD V SS CLK GW BWE OE ADSC ADSP ADV A A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 7...

Page 3: ...ns OE is masked during the first clock of a Read cycle when emerging from a deselected state ADV Input Synchronous Advance Input signal sampled on the rising edge of CLK active LOW When asserted it automatically increments the address in a burst cycle ADSP Input Synchronous Address Strobe from Processor sampled on the rising edge of CLK active LOW When asserted LOW A is captured in the address reg...

Page 4: ...esented to the DQ inputs is written into the corre sponding address location in the memory array If GW is HIGH then the Write operation is controlled by BWE and BW A D signals The CY7C1218H provides Byte Write capability that is described in the Write Cycle Descriptions table Asserting the Byte Write Enable input BWE with the selected Byte Write BW A D input will selectively write to only the desi...

Page 5: ...DQ Read Continue Read Next L H X X X H L H Tri State Read Continue Read Next L H X X X H L L DQ Read Suspend Read Current L X X X H H H H Tri State Read Suspend Read Current L X X X H H H L DQ Read Suspend Read Current L H X X X H H H Tri State Read Suspend Read Current L H X X X H H L DQ Read Begin Write Current L X X X H H H X Tri State Write Begin Write Current L H X X X H H X Tri State Write B...

Page 6: ...Write Byte A DQA and DQPA H L H H H L Write Byte B DQB and DQPB H L H H L H Write Bytes B A H L H H L L Write Byte C DQC and DQPC H L H L H H Write Bytes C A H L H L H L Write Bytes C B H L H L L H Write Bytes C B A H L H L L L Write Byte D DQD and DQPD H L L H H H Write Bytes D A H L L H H L Write Bytes D B H L L H L H Write Bytes D B A H L L H L L Write Bytes D C H L L L H H Write Bytes D C A H ...

Page 7: ... 8 for 3 3V I O 2 0 VDD 0 3V V for 2 5V I O 1 7 VDD 0 3V V VIL Input LOW Voltage 8 for 3 3V I O 0 3 0 8 V for 2 5V I O 0 3 0 7 V IX Input Leakage Current except ZZ and MODE GND VI VDDQ 5 5 µA Input Current of MODE Input VSS 30 µA Input VDD 5 µA Input Current of ZZ Input VSS 5 µA Input VDD 30 µA IOZ Output Leakage Current GND VI VDDQ Output Disabled 5 5 µA IDD VDD Operating Supply Current VDD Max I...

Page 8: ...ow standard test methods and procedures for measuring thermal impedance per EIA JESD51 30 32 C W ΘJC Thermal Resistance Junction to Case 6 85 C W AC Test Loads and Waveforms Note 10 Tested initially and after any design or process change that may affect these parameters OUTPUT R 317Ω R 351Ω 5 pF INCLUDING JIG AND SCOPE a b OUTPUT RL 50Ω Z0 50Ω VT 1 5V 3 3V ALL INPUT PULSES VDDQ GND 90 10 90 10 1 n...

Page 9: ...se 0 5 0 5 ns tADH ADSP ADSC Hold after CLK Rise 0 5 0 5 ns tADVH ADV Hold after CLK Rise 0 5 0 5 ns tWEH GW BWE BW A D Hold after CLK Rise 0 5 0 5 ns tDH Data Input Hold after CLK Rise 0 5 0 5 ns tCEH Chip Enable Hold after CLK Rise 0 5 0 5 ns Notes 11 Timing references level is 1 5V when VDDQ 3 3V and is 1 25V when VDDQ 2 5V 12 Test conditions shown in a of AC Test Loads unless otherwise noted 1...

Page 10: ...r CE3 is HIGH tCYC t CL CLK ADSP t ADH t ADS ADDRESS t CH OE ADSC CE tAH tAS A1 tCEH tCES GW BWE BW A D Data Out Q High Z tCLZ tDOH tCO ADV tOEHZ tCO Single READ BURST READ tOEV tOELZ tCHZ ADV suspends burst Burst wraps around to its initial state tADVH tADVS tWEH tWES tADH tADS Q A2 Q A2 1 Q A2 2 Q A1 Q A2 Q A2 1 Q A2 3 A2 A3 Deselect cycle Burst continued with new base address DON T CARE UNDEFIN...

Page 11: ...tADS ADDRESS tCH OE ADSC CE tAH tAS A1 tCEH tCES BWE BW A D Data Out Q High Z ADV BURST READ BURST WRITE D A2 D A2 1 D A2 1 D A1 D A3 D A3 1 D A3 2 D A2 3 A2 A3 Data In D Extended BURST WRITE D A2 2 Single WRITE tADH tADS tADH tADS t OEHZ t ADVH t ADVS tWEH tWES tDH tDS GW tWEH tWES Byte write signals are ignored for first cycle when ADSP initiates burst ADSC extends burst ADV suspends burst DON T...

Page 12: ...le is performed 20 GW is HIGH Switching Waveforms continued tCYC tCL CLK ADSP tADH tADS ADDRESS tCH OE ADSC CE tAH tAS A2 tCEH tCES BWE BW A D Data Out Q High Z ADV Single WRITE D A3 A4 A5 A6 D A5 D A6 Data In D BURST READ Back to Back READs High Z Q A2 Q A1 Q A4 Q A4 1 Q A4 2 tWEH tWES Q A4 3 tOEHZ tDH tDS tOELZ tCLZ tCO Back to Back WRITEs A1 DON T CARE UNDEFINED A3 Feedback ...

Page 13: ... entering ZZ mode See Cycle Descriptions table for all possible signal conditions to deselect the device 22 DQs are in High Z when exiting ZZ sleep mode Switching Waveforms continued t ZZ I SUPPLY CLK ZZ t ZZREC ALL INPUTS except ZZ DON T CARE I DDZZ t ZZI tRZZI Outputs Q High Z DESELECT or READ Only Feedback ...

Page 14: ...ve or visit www cypress com for actual products offered Speed MHz Ordering Code Package Diagram Package Type Operating Range 100 CY7C1218H 100AXC 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Commercial CY7C1218H 100AXI Industrial 133 CY7C1218H 133AXC 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Commercial CY7C1218H 133AXI Industrial Feedback ...

Page 15: ... failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Package Diagram NOTE 1 JEDEC STD REF MS 026 2 BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION END FLASH MOLD PROTRUSION END FLAS...

Page 16: ...poration on Page 1 from 3901 North First Street to 198 Champion Court Added 2 5VI O option Changed Three State to Tri State Included Maximum Ratings for VDDQ relative to GND Modified Input Load to Input Leakage Current except ZZ and MODE in the Electrical Characteristics Table Modified test condition from VIH VDD to VIH VDD Replaced Package Name column with Package Diagram in the Ordering Informat...

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