CY7C1024DV33
Document Number: 001-08353 Rev. *C
Page 5 of 9
Write Cycle
[9, 10]
t
WC
Write Cycle Time
10
ns
t
SCE
CE
active LOW to Write End
[3]
7
ns
t
AW
Address Setup to Write End
7
ns
t
HA
Address Hold from Write End
0
ns
t
SA
Address Setup to Write Start
0
ns
t
PWE
WE Pulse Width
7
ns
t
SD
Data Setup to Write End
5.5
ns
t
HD
Data Hold from Write End
0
ns
t
LZWE
WE HIGH to Low Z
[7]
3
ns
t
HZWE
WE LOW to High Z
[7]
5
ns
Data Retention Characteristics
Over the Operating Range
Parameter
Description
Conditions
[3]
Min
Typ
Max
Unit
V
DR
V
CC
for Data Retention
2
V
I
CCDR
Data Retention Current
V
CC
= 2V, CE > V
CC
– 0.2V,
V
IN
> V
CC
– 0.2V or V
IN
< 0.2V
25
mA
t
CDR
[11]
Chip Deselect to Data Retention Time
0
ns
t
R
[12]
Operation Recovery Time
t
RC
ns
Data Retention Waveform
AC Switching Characteristics
(continued)
Over the Operating Range
[5]
Parameter
Description
–10
Unit
Min
Max
3.0V
3.0V
t
CDR
V
DR
>
2V
DATA RETENTION MODE
t
R
CE
V
CC
Notes
9. The internal write time of the memory is defined by the overlap of CE
1
and CE
2
and CE
3
LOW and WE LOW. Chip enables must be active and WE must be LOW to
initiate a write. The transition of any of these signals terminate the write. The input data setup and hold timing is referenced to the leading edge of the signal that
terminates the write.
10. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
11. Tested initially and after any design or process changes that may affect these parameters.
12. Full device operation requires linear V
CC
ramp from V
DR
to V
CC(min)
> 50
μ
s or stable at V
CC(min)
> 50
μ
s.
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