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128K x 8 Static RAM

CY7C1018CV33

Cypress Semiconductor Corporation

198 Champion Court

San Jose

,

CA 95134-1709

408-943-2600

Document #: 38-05131 Rev. *D

 Revised August 3, 2006

Features

• Pin- and function-compatible with CY7C1018BV33
• High  speed

— t

AA

 = 10 ns 

• CMOS for optimum speed/power
• Center power/ground pinout
• Data retention at 2.0V
• Automatic power-down when deselected
• Easy memory expansion with CE

 

and OE options

• Available in Pb-free and non Pb-free 300-mil-wide 

32-pin SOJ

Functional Description

[1]

The CY7C1018CV33 is a high-performance CMOS static
RAM organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and tri-state drivers. This

device has an automatic power-down feature that significantly
reduces power consumption when deselected. 

Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O

0

 through I/O

7

) is then written into the location

specified on the address pins (A

0

 through A

16

).

Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.

The eight input/output pins (I/O

0

 through I/O

7

) are placed in a

high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).

The CY7C1018CV33 is available in a standard 300-mil-wide
SOJ.

Note:

1.

For guidelines on SRAM system designs, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.

14

15

Logic Block Diagram

Pin Configurations

A

1

A

2

A

3

A

4

A

5

A

6

A

7

A

8

COLUMN

DECODER

ROW DE

CODER

SENSE A

M

PS

INPUT BUFFER

POWER

DOWN

WE

OE

I/O

0

I/O

1

I/O

2

I/O

3

ARRAY

I/O

7

I/O

6

I/O

5

I/O

4

A

0

A

11

A

13

A

12

A

A

10

CE

A

A

16

A

9

1

2
3

4

5
6

7
8
9
10
11

14

19

20

24

23
22
21

25

28

27
26

Top View

SOJ

12

13

29

32

31
30

16

15

17

18

A

7

A

1

A

2

A

3

CE

I/O

0

I/O

1

V

CC

A

13

A

16

A

15

OE
I/O

7

I/O

6

A

12

A

11

A

10

A

9

I/O

2

A

0

A

4

A

5

A

6

I/O

4

V

CC

I/O

5

A

8

I/O

3

WE

V

SS

A

14

V

SS

128K x 8

[+] Feedback 

Summary of Contents for CY7C1018CV33

Page 1: ...cation specified on the address pins A0 through A16 Reading from the device is accomplished by taking Chip Enable CE and Output Enable OE LOW while forcing Write Enable WE HIGH Under these conditions...

Page 2: ...Conditions 10 12 15 Unit Min Max Min Max Min Max VOH Output HIGH Voltage VCC Min IOH 4 0 mA 2 4 2 4 2 4 V VOL Output LOW Voltage VCC Min IOL 8 0 mA 0 4 0 4 0 4 V VIH Input HIGH Voltage 2 0 VCC 0 3 2...

Page 3: ...for all speeds are tested using the Th venin load shown in Figure a High Z characteristics are tested for all speeds using the test load shown in Figure c 5 Test conditions assume signal transition ti...

Page 4: ...r to or coincident with CE transition LOW 14 Data I O is high impedance if OE VIH 15 If CE goes HIGH simultaneously with WE going HIGH the output remains in a high impedance state PREVIOUS DATA VALID...

Page 5: ...VALID CE ADDRESS WE DATA I O OE NOTE 16 DATA VALID tHD tSD tLZWE tPWE tSA tHA tAW tSCE tWC tHZWE CE ADDRESS WE DATA I O NOTE 16 Truth Table CE OE WE I O0 I O7 Mode Power H X X High Z Power down Stand...

Page 6: ...ents in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application...

Page 7: ...Loads split based on speed B 115046 05 30 02 HGK ICC and ISB1 modified C 116476 09 16 02 CEA Add applications foot note on data sheet pg 1 D 493543 See ECN NXR Added Industrial Operating Range Removed...

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