CY7C09079V/89V/99V
CY7C09179V/89V/99V
Document #: 38-06043 Rev. *C
Page 16 of 21
Figure 17. Counter Reset (Pipelined Outputs)
[19, 26, 32, 33]
Notes
32. CE
0
= V
IL
; CE
1
= V
IH
.
33. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset.
Switching Waveforms
(continued)
t
CH2
t
CL2
t
CYC2
CLK
ADDRESS
INTERNAL
CNTEN
ADS
DATA
IN
ADDRESS
CNTRST
R/W
DATA
OUT
Q
0
Q
1
Q
n
D
0
A
X
0
1
A
n
A
n+1
t
SAD
t
HAD
t
SCN
t
HCN
t
SRST
t
HRST
t
SD
t
HD
t
SW
t
HW
A
n
A
n+1
t
SA
t
HA
COUNTER
RESET
WRITE
ADDRESS 0
READ
ADDRESS 0
READ
ADDRESS 1
READ
ADDRESS n
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