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Document Number: 38-07135  Rev. *B

Revised August 07, 2007

Page 11 of 11

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CY7B9910
CY7B9920

© Cypress Semiconductor Corporation, 2001-2007.The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
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Document History

Document Title: CY7B9910/CY7B9920 Low Skew Clock Buffer
Document Number: 38-07135

REV.

ECN NO.

Issue Date

Orig. of 
Change

Description of Change

**

110244

10/28/01

SZV

Change from Specification number: 38-00437 to 38-07135

*A

1199925

See ECN

DPF/AESA Added Pb-free parts in Ordering Information

Added Note 20: Not recommended for the new design

*B

1353343

See ECN

AESA

Change status to final

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Summary of Contents for CY7B9910

Page 1: ...9920 CMOS The completely integrated PLL enables zero delay capability External divide capability combined with the internal PLL allows distribution of a low frequency clock that is multiplied by virtu...

Page 2: ...o one of the eight outputs FS 1 2 3 I Three level frequency range select TEST I Three level select See TEST MODE Q 0 7 O Clock outputs VCCN PWR Power supply for output drivers VCCQ PWR Power supply fo...

Page 3: ...orage Temperature 65 C to 150 C Ambient Temperature with Power Applied 55 C to 125 C Supply Voltage to Ground Potential 0 5V to 7 0V DC Input Voltage 0 5V to 7 0V Output Current into Outputs LOW 64 mA...

Page 4: ...l 85 85 mA Mil Ind 90 90 ICCN Output Buffer Current per Output Pair 6 VCCN VCCQ Max IOUT 0 mA Input Selects Open fMAX 14 19 mA PD Power Dissipation per Output Pair 7 VCCN VCCQ Max IOUT 0 mA Input Sel...

Page 5: ...pF CL 30 pF for 5 and 2devices Includes fixture and probe capacitance VCC Switching Characteristics Over the Operating Range 11 CY7B9910 2 8 CY7B9920 2 8 Parameter Description Min Typ Max Min Typ Max...

Page 6: ...he CY7B9920 are CMOS levels VCC 2 to VCC 2 Test conditions assume signal transition times of 2ns or less and output loading as shown in the AC Test Loads and Waveforms unless otherwise specified 12 Ex...

Page 7: ...HIGH 5 0 5 0 ns tRPWL REF Pulse Width LOW 5 0 5 0 ns tSKEW Zero Output Skew All Outputs 13 14 0 3 0 75 0 3 0 75 ns tDEV Device to Device Skew 8 15 1 5 1 5 ns tPD Propagation Delay REF Rise to FB Rise...

Page 8: ...C Timing Diagrams Figure 1 AC Timing Diagrams Figure 2 Zero Skew and Zero Delay Clock Driver tODCV tODCV tREF REF FB Q OTHERQ tRPWH tRPWL tPD tSKEW tSKEW tJR SYSTEM CLOCK FB REF FS Q0 Q1 Q2 Q3 Q4 Q5 Q...

Page 9: ...ew speci fication coupled with the ability to drive terminated transmission lines with impedances as low as 50 ohms enables efficient printed circuit board design Figure 1 shows the CY7B9910 9920 conn...

Page 10: ...Y7B9920 5SI 24 Pb Small Outline IC Industrial 750 CY7B9910 7SC 24 Pb Small Outline IC Commercial CY7B9910 7SI 20 24 Pb Small Outline IC Industrial CY7B9920 7SC 20 24 Pb Small Outline IC Commercial CY7...

Page 11: ...otection United States and foreign United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modi...

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