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CY62167EV30 MoBL

®

Document #: 38-05446 Rev. *E

Page 6 of 14

Switching Waveforms

Figure 5

 shows address transition controlled read cycle waveforms.

[19, 20]

Figure 5.  Read Cycle No. 1

Figure 6

 shows OE controlled read cycle waveforms.

[20, 21]

Figure 6.  Read Cycle No. 2

PREVIOUS DATA VALID

DATA VALID

RC

t

AA

t

OHA

t

RC

ADDRESS

DATA OUT

50%

50%

DATA VALID

t

RC

t

ACE

t

DOE

t

LZOE

t

LZCE

t

PU

HIGH IMPEDANCE

t

HZOE

t

PD

t

HZBE

t

LZBE

t

HZCE

t

DBE

OE

CE

1

ADDRESS

CE

2

BHE/BLE

DATA OUT

V

CC

SUPPLY

CURRENT

HIGH 

I

CC

I

SB

IMPEDANCE

Notes

19. The device is continuously selected. OE, CE

= V

IL

, BHE, BLE or both = V

IL

, and CE

= V

IH

.

20. WE is HIGH for read cycle.
21. Address valid before or similar to CE

1

, BHE, BLE transition LOW and CE

2

 transition HIGH.

[+] Feedback 

Summary of Contents for CY62167EV30

Page 1: ...HIGH The input and output pins I O0 through I O15 are placed in a high impedance state when the device is deselected CE1 HIGH or CE2 LOW outputs are disabled OE HIGH both Byte High Enable and Byte Lo...

Page 2: ...21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A15 A14 A13 A12 A11 A10 A9 A8 A19 NC WE CE2 NC BHE BLE A18 A17 A7 A6 A5 A4 A3 A2 A1 A16 BYTE Vss IO15 A20 IO7 IO14...

Page 3: ...package 0 3 0 7 9 V IIX Input Leakage Current GND VI VCC 1 1 A IOZ Output Leakage Current GND VO VCC Output Disabled 1 1 A ICC VCC Operating Supply Current f fMAX 1 tRC VCC VCC max IOUT 0 mA CMOS leve...

Page 4: ...V ICCDR 10 Data Retention Current VCC 1 5V to 3 0V CE1 VCC 0 2V CE2 0 2V VIN VCC 0 2V or VIN 0 2V Industrial Auto A 45ZXI TSOP I 8 A VCC 1 5V CE1 VCC 0 2V CE2 0 2V VIN VCC 0 2V or VIN 0 2V Industrial...

Page 5: ...tSD Data Setup to Write End 25 ns tHD Data Hold from Write End 0 ns tHZWE WE LOW to High Z 16 17 18 ns tLZWE WE HIGH to Low Z 16 10 ns Notes 14 Test conditions for all parameters other than tri state...

Page 6: ...PREVIOUS DATA VALID DATA VALID RC tAA tOHA tRC ADDRESS DATA OUT 50 50 DATA VALID tRC tACE tDOE tLZOE tLZCE tPU HIGH IMPEDANCE tHZOE tPD tHZBE tLZBE tHZCE tDBE OE CE1 ADDRESS CE2 BHE BLE DATA OUT VCC S...

Page 7: ...rms continued tHD tSD tPWE tSA tHA tAW tSCE tWC tHZOE VALID DATA tBW NOTE 24 CE1 ADDRESS CE2 WE DATA I O OE BHE BLE Notes 22 Data IO is high impedance if OE VIH 23 If CE1 goes HIGH and CE2 goes LOW si...

Page 8: ...le No 2 Figure 9 shows WE controlled OE LOW write cycle waveforms 23 Figure 9 Write Cycle No 3 Switching Waveforms continued tHD tSD tPWE tHA tAW tSCE tWC tHZOE VALID DATA tBW tSA NOTE 24 CE1 ADDRESS...

Page 9: ...Read Active ICC L H H L H L Data Out I O0 I O7 High Z I O8 I O15 Read Active ICC L H H L L H High Z I O0 I O7 Data Out I O8 I O15 Read Active ICC L H H H L H High Z Output Disabled Active ICC L H H H...

Page 10: ...62167EV30LL 45BVXI 51 85150 48 ball VFBGA 6 x 8 x 1 mm Pb free CY62167EV30LL 45ZXI 51 85183 48 pin TSOP I Pb free CY62167EV30LL 45ZXA 51 85183 48 pin TSOP I Pb free Automotive A Shaded areas contain p...

Page 11: ...continued A 1 A1 CORNER 0 75 0 75 0 30 0 05 48X 0 25 M C A B 0 05 M C B A 0 15 4X 0 21 0 05 1 00 MAX C SEATING PLANE 0 55 MAX 0 25 C 0 10 C A1 CORNER TOP VIEW BOTTOM VIEW 2 3 4 3 75 5 25 B C D E F G H...

Page 12: ...ge Diagrams continued 1 N 0 020 0 50 0 007 0 17 0 037 0 95 0 002 0 05 0 5 MAX 0 028 0 70 0 010 0 25 0 004 0 10 0 011 0 27 0 041 1 05 0 047 1 20 0 472 12 00 0 724 18 40 0 787 20 00 0 006 0 15 TYP 0 020...

Page 13: ...Changed tLZOE from 3 ns to 5 ns Changed tHZOE tHZCE tHZBE and tHZWE from 15 ns to 18 ns Changed tSCE tAW and tBW from 40 ns to 35 ns Changed tPE from 30 ns to 35 ns Changed tSD from 20 ns to 25 ns Up...

Page 14: ...firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation...

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