CY62167EV30 MoBL
®
16-Mbit (1M x 16 / 2M x 8) Static RAM
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Document #: 38-05446 Rev. *E
Revised March 23, 2009
Features
■
TSOP I Package Configurable as 1M x 16 or 2M x 8 SRAM
■
Very High Speed: 45 ns
■
Temperature Ranges
❐
Industrial: –40°C to +85°C
❐
Automotive-A: –40°C to +85°C
■
Wide Voltage Range: 2.20V to 3.60V
■
Ultra Low Standby Power
❐
Typical standby current: 1.5
μ
A
❐
Maximum standby current: 12
μ
A
■
Ultra Low Active Power
❐
Typical active current: 2.2 mA @ f = 1 MHz
■
Easy Memory Expansion with CE
1
, CE
2
, and OE Features
■
Automatic Power Down when Deselected
■
CMOS for Optimum Speed and Power
■
Offered in Pb-free 48-Ball VFBGA and 48-Pin TSOP I
Packages
Functional Description
The CY62167EV30 is a high performance CMOS static RAM
organized as 1M words by 16 bits or 2M words by 8 bits. This
device features an advanced circuit design that provides an ultra
low active current. Ultra low active current is ideal for providing
More Battery Life
™
(MoBL
®
) in portable applications such as
cellular telephones. The device also has an automatic power
down feature that reduces power consumption by 99 percent
when addresses are not toggling. Place the device into standby
mode when deselected (CE
1
HIGH or CE
2
LOW or both BHE and
BLE are HIGH). The input and output pins (I/O
0
through I/O
15
)
are placed in a high impedance state when: the device is
deselected (CE
1
HIGH or CE
2
LOW), outputs are disabled (OE
HIGH), both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH), or a write operation is in progress (CE
1
LOW,
CE
2
HIGH and WE LOW).
To write to the device, take Chip Enables (CE
1
LOW and CE
2
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
) is
written into the location specified on the address pins (A
0
through
A
19
). If Byte High Enable (BHE) is LOW, then data from the I/O
pins (I/O
8
through I/O
15
) is written into the location specified on
the address pins (A
0
through A
19
).
To read from the device, take Chip Enables (CE
1
LOW and CE
2
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appears
on I/O
0
to I/O
7
. If Byte High Enable (BHE) is LOW, then data from
memory appears on I/O
8
to I/O
15
. See the
“Truth Table” on
page 9
for a complete description of read and write modes.
For best practice recommendations, refer to the Cypress
application note
AN1064, SRAM System Guidelines
.
1M × 16 / 2M x 8
RAM Array
IO
0
–IO
7
ROW DECODER
A
8
A
7
A
6
A
5
A
2
COLUMN DECODER
A
11
A
12
A
13
A
14
A
15
SENSE AMPS
DATA IN DRIVERS
OE
A
4
A
3
IO
8
–IO
15
WE
BLE
BHE
A
16
A
0
A
1
A
17
A
9
A
18
A
10
CE
2
CE
1
A
19
BYTE
Power Down
Circuit
BHE
BLE
CE
2
CE
1
Logic Block Diagram
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