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Document Number: 001-51592 Rev. **

Revised March 04, 2009

Page 16 of 16

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STK14CA8

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Document Title: STK14CA8 128Kx8 AutoStore™ nvSRAM
Document Number: 001-51592

Revision

ECN

Orig. of 

Change

Submission 

Date

Description of Change

**

2665610

GVCH/PYRS

02/04/09

New data sheet 

[+] Feedback 

Summary of Contents for AutoStore STK14CA8

Page 1: ...ment included with each memory cell This SRAM provides fast access and cycle times ease of use and unlimited read and write endurance of a normal SRAM Data transfers automatically to the nonvolatile s...

Page 2: ...ddress inputs select one of 131 072 bytes in the nvSRAM array DQ7 DQ0 I O Data Bi directional 8 bit data bus for accessing the nvSRAM E Input Chip Enable The active low E input selects the device W In...

Page 3: ...CC Current 65 55 50 70 60 55 mA mA mA tAVAV 25 ns tAVAV 35 ns tAVAV 45 ns Dependent on output loading and cycle rate Values obtained without output loads ICC2 Average VCC Current during STORE 3 3 mA A...

Page 4: ...C f 1 0 MHz Figure 4 AC Output Loading Figure 5 AC Output Loading for Tristate Specifications tHZ tLZ tWLQZ tWHQZ tGLQX tGHQZ Symbol Parameter 2 Max Units Conditions CIN Input Capacitance 7 pF V 0 to...

Page 5: ...put Hold after Address Change 3 3 3 ns 6 tELQX tLZ Address Change or Chip Enable to Output Active 3 3 3 ns 7 tEHQZ 5 tHZ Address Change or Chip Disable to Output Inactive 10 13 15 ns 8 tGLQX tOLZ Outp...

Page 6: ...s 17 tAVWH tAVEH tAW Address Setup to End of Write 20 25 30 ns 18 tAVWL tAVEL tAS Address Setup to Start of Write 0 0 0 ns 19 tWHAX tEHAX tWR Address Hold after End of Write 0 0 0 ns 20 tWLQZ 5 7 tWZ...

Page 7: ...its Notes Standard Alternate Min Max 22 tHRECALL Power up RECALL Duration 20 ms 9 23 tSTORE tHLHZ STORE Cycle Duration 12 5 ms 10 11 24 VSWITCH Low Voltage Trigger Level 2 65 V 25 VCCRISE VCC Rise Tim...

Page 8: ...LL Initiation Cycle Time 25 35 45 ns 13 27 tAVEL tAVGL tAS Address Setup Time 0 0 0 ns 28 tELEH tGLGH tCW Clock Pulse Width 20 25 30 ns 29 tEHAX tGHAX Address Hold Time 1 1 1 ns 30 tRECALL tRECALL REC...

Page 9: ...31 NO Symbols Parameter STK14CA8 Units Notes Standard Min Max 33 tSS Soft Sequence Processing Time 70 s 15 16 33 33 Notes 14 On a hardware STORE initiation SRAM operation continues to be enabled for...

Page 10: ...Output Data Output Data Active 17 18 19 L H L 0x04E38 0x0B1C7 0x083E0 0x07C1F 0x0703F Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Output Data Output Data Output Data Output Data Output Data Acti...

Page 11: ...is enabled by default on the STK14CA8 During normal operation the device draws current from VCC to charge a capacitor connected to the VCAP pin This stored charge is used by the chip to perform a sing...

Page 12: ...areful routing of power ground and signals reduce circuit noise Best Practices nvSRAM products have been used effectively for over 15 years While ease of use is one of the product s main system values...

Page 13: ...rmed in a manner similar to the software STORE initi ation To initiate the AutoStore Disable sequence the following sequence of E controlled or G controlled READ operations must be performed The AutoS...

Page 14: ...RAM SSOP48 300 35 ns Commercial STK14CA8 RF45 3V 128Kx8 AutoStore nvSRAM SSOP48 300 45 ns Commercial STK14CA8 RF25TR 3V 128Kx8 AutoStore nvSRAM SSOP48 300 25 ns Commercial STK14CA8 RF35TR 3V 128Kx8 Au...

Page 15: ...STK14CA8 Document Number 001 51592 Rev Page 15 of 16 Package Diagrams Figure 17 32 Pin 300 mil SOIC 51 85127 Figure 18 48 Pin 300 mil SSOP 51 85061 51 85127 A 51 85061 C Feedback...

Page 16: ...it as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express writ...

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