Curtiss-Wright SCRAMNet+ SC150e, Hardware Reference Manual

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SCRAMNET OVERVIEW
Copyright 2007 2-5 S SC150e HARDWARE REFERENCE
PLUS MODES
The PLUS mode protocol enhancement can increase the maximum network throughput
from 6.5 MB/sec to approximately 15.2 to 16.7 MB/sec by the use of variable-length
message packets. Each S SC150e message packet has a 46-bit header plus
the data. The user-selectable maximum message packet size increases the data size from
the normal 32 bits to either 256 or 1024 bytes of data. Data must be written to sequential
longword addresses.
2.5 Auxiliary Control RAM (ACR)
The Auxiliary Control RAM (ACR) provides external triggering and interrupt control by
offering a choice of four actions to occur when a particular S SC150e shared-
memory address is written into. Each shared-memory location has its own action or set of
actions associated with it.
0
1
Shared Memory
ACR Memory
CSR0[4]
Host READ/WRITE
request to a specific
32-bit memory address
Byte 0 Byte 1
Byte 2 Byte 3
Byte 0
PHYSICAL
MEMORY CHIP
DOES NOT
REALLY EXIST
LEGEND
Figure 2-2 ACR/Memory Access
In Figure 2-2, host CPU read/write operations are channeled to either S
SC150e memory or to the ACR. The ACR is a physically separate memory from the
shared memory. Channeling is based on a user-controlled switch setting and may be
toggled to the desired position by writing to a bit in the S SC150e CSR.
When access to the ACR is enabled, shared memory is not accessible by the host and the
ACR byte is viewed as the least significant byte (LSB) of every shared-memory four -
byte address. The ACR bits define the necessary external trigger and/or interrupt action(s)
taken whenever writing to any byte of the S SC150e shared-memory four-
byte word.
Only five bits of the ACR are associated with every four-byte word of shared memory
(on even four-byte boundaries). The other 27 bits of the ACR are not used .