Curtiss-Wright GT200, Hardware Reference Manual

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COUNTER/TIMER DEFINITIONS
B.1 Counter/Timer Definitions
Counter/Timer Definition
NET_TMR Network timer. This timer is incremented on every network
transmit clock period. For 2.5 Gbps product configurations,
the network transmit clock period is 8 ns and rolls over
approximately every 34.4 s.
HST_TMR Host timer. This timer is incremented on every host bus clock
period. For 66 MHz PCI product configurations, the host bus
clock period is approximately 15.2 ns and rolls over
approximately every 65.2 s.
LAT_TMR Latency timer: This timer measures transit latency. The timer
begins counting on transmission of the auto-message and
stops counting on receipt of a native auto-message. The
latency is incremented on every network transmit clock period
that the native auto-message is in transit. For 2.5 Gbps
product configurations, the network transmit clock period is
8ns and rolls over approximately every 34.4 s.
SM_TRFC_CNTR Shared Memory Traffic counter. This counter is incremented
on every reception of 32-bit network shared memory data
phase (native or foreign). Note that network memory traffic
representing network traffic of less than 32-bits are treated
like 32-bits for purposes of counting network traffic.
INT_TRFC_CNTR Interrupt Traffic counter. This counter is incremented on
every reception of network interrupt traffic (native or foreign).
HNT_TRFC_CNTR Hunt Traffic counter. This counter is incremented on every
reception of 32-bit network shared memory data phase from
the node ID specified by the HNT_ID field to the LNK_CTL
register. Note that network memory traffic representing
network traffic of less than 32-bits are treated like 32-bits for
purposes of counting network traffic. Note also that this
counter only counts shared memory traffic from the specified
node and not network interrupt traffic.
NHIQ_INT_CNTR Network Interrupt counter. This counter is incremented on
every network interrupt that has been placed into the NHIQ.
This value gives a total number of interrupt received and the
lowest bits (8 for a queue of 256) give the effective address of
the next interrupt location within the queue, allowing the
current position of the last interrupt data to be determined by
subtracting 1.
HST_INT_CNTR Host Interrupt counter. This counter is incremented on every
new assertion of a host interrupt request.
LNK_ERR_CNTR Link Error counter. This counter is incremented on every
network error (including decoder error, synchronization error,
CRC error, EOF error, protocol error, RXF error, and
transition of link down).
LNK_DOWN_CNTR Link Down counter. This counter is incremented on transition
of a link down.
DEC_ERR_CNTR Decoder Error counter. This counter is incremented on every
8b/10b decoding error.
Copyright 2005 B-1 GT200 Hardware Reference