OPERATION
4.4 Host Hardware
4.4.1 Target Interface
4.4.1.1 Control plane
The control plane supports control and status of both host and link interfaces via Control
and Status Registers.
4.4.1.2 Data plane.
The data plane can also be used to access shared memory and initiate network traffic. The
target interface may be accessed by the host microprocessor (via PIO operations) or by
another PCI card (via peer-to-peer DMA initiated by the other board’s DMA controller).
4.4.2 Initiator Interface
4.4.2.1 Data Plane.
The initiator interface may be used to access shaired memory for DMA to other boards’
target interface.
4.4.3 Bus Support
The hardware supports 33 MHz/66 MHz PCI operation for both 32-bit and 64-bit buses.
The hardware supports 3.3-volt PCI signaling voltages.
4.4.4 5-Volt PCI Bus Support
The PCI to PMC adapter card has been designed specifically for 5-volt legacy
environments. Many users are still using older PCI-based machines that only support
5-volt PCI signaling voltages. By installing a GT200 PMC board onto the 5-volt PCI to
PMC adapter
the user now has a 5-volt signaling PCI board that can be used in older
legacy systems.
4.4.5 Byte Swapping
The hardware contains steering logic supporting both Little Endian and Big Endian
accesses for the target and initiator interfaces. The byte-swapping logic also includes the
ability to swap 32-bit words within a 64-bit access. The target and initiator logic contain
independent settings for the byte and word (32-bit) swapping.
4.4.6 Interrupt Support
The hardware supports both network and applicable host interrupts.
No interrupts are generated by the hardware until explicitly enabled by the software
(driver and/or user).
Network interrupts (HBI and HUI) may be initiated via PIO accesses (via the appropriate
SW function) or via an interrupt flag on DMA operations.
Separate target locations for each HBI and HUI interrupt avoid the necessity of a
semaphore for network interrupt initiation.
Copyright 2005
4-9
GT200
Hardware Reference
Summary of Contents for GT200
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