CDR-3250/80 TECHNICAL MANUAL
Issue 2.2
4-3
The signal leaves the module as the 1ST LO at 40.456 -
70.456 MHz in 1 kHz steps at a level of +10 dBm.
A fault detector sends the OUTPUT/FINE FAULT signal to
the digital module if the output or fine loops lose lock.
4-2.5.4
2nd/3rd LO REF Generation.
One path of the
internal or external reference frequency signal is amplified
and used as the 2nd/3rd LO REF signal at 10 MHz for
application to the RF Analog module. The other path is
split and used as the reference frequency for the fine and
step loop PLL circuits.
4-2.5.5
Audio.
The audio circuits are located in a separate
shielded compartment in the synthesizer module. The
shielding prevents interaction between the high-level audio
and sensitive VCO circuits.
The NORM AUDIO and ALT AUDIO signals from the DSP
Section in the Digital module are applied to the audio
board. The ALT AUDIO signal supplies LSB audio during
ISB mode operation only.
Audio from each of these inputs is applied directly to two
line amplifiers. These amplifiers are used for the NORM
and ALT line audio outputs. The line amplifiers are
transformer coupled to achieve the desired balanced
output. The line output levels are adjustable using
potentiometers.
The audio inputs are also applied to an audio selector
switch to route the desired audio signal to a third amplifier.
This amplifier is used for the front panel PHONES jack. The
amplifier's output is single-ended and protected by
resistors. The VOL CONTROL voltage for the phones
amplifier is supplied from the front panel volume control.
During the BITE check, the audio signal is sensed by an
audio detector. If the detector does not sense a signal
during the test, the /DET AUDIO signal is not sent to the
Control Section in the Digital module. The Control Section
then causes the fault to be displayed, and stores it in
memory. The speaker audio is disabled during the BITE
check of the power-on self test (POST), but enabled during
the operator selected BITE check. (Refer to paragraph 5-
5.2).
4-2.6
Digital Module.
The Digital module contains two
major sections: the Control Section, and the DSP Section.
Each of these sections is described below.
4-2.6.1
Control Section.
The Control Section governs all
aspects of the receiver's operation. The Control Section
receives commands from the operator through the keypad
or from the optional remote control bus, and provides
status and data information to the operator through the
front panel display and the remote control bus. All receiver
operating parameters, such as frequency, mode, IF
bandwidth, and gain are directly controlled by the Control
Section. In addition, the Control Section can store up to
250 different sets of operating parameters into memory
channels. These memory channels can be recalled
individually, scanned sequentially, or used in pairs as band
limits for frequency sweeps. The current operating
parameters and the 250 memory channels are stored in non-
volatile memory and are retained when power is removed.
The Control Section contains a microprocessor containing
a 16-bit internal data bus, with an 8-bit external bus. The
clock frequency is 16 MHz using an external 32 MHz
crystal. The program is stored in a 128k x 8-bit flash
memory, and data memory consists of a 32k x 8-bit static
RAM IC. Channel memory and other miscellaneous non-
volatile storage requirements are provided by an 8k x 8-bit
EEPROM.
An encoder logic circuit receives data inputs from the front
panel adjustment knob optical shaft encoder. The shaft
encoder is mounted on the shaft of the knob and produces
two signals used to determine the amount and direction of
knob rotation. The keypad encoder provides the interface
between the front panel keypad and the Control Section.
A key press is sensed as an interrupt input to the
processor. The full graphic vacuum fluorescent display in
the front panel contains a processor bus interface con-
necting directly to the buffered data bus.
I/O ports provide all processor output to the analog and
DSP sections of the receiver. D-latches are clocked by
decoded addresses gated with a processor write signal.
Some of these latched output lines are grouped together as
enable, clock, and data lines and are operated by the
processor as synchronous serial ports. Other latched
output lines are used as direct control signals.
I/O signals include:
/FAULTs
Input from the modules indicating
a fault condition.
/DET AUDIO
Input from Audio board in
Synthesizer module to determine if
BITE signals pass completely
through receiver circuits.
CMD FLAG
Informs the DSP Section that the
command register contains a CMD
MSG ready for transfer.
CMD MSG
Control data from the Control
Section to the DSP Section.
Courtesy of http://BlackRadios.terryo.org
