CDR-3250/80 TECHNICAL MANUAL
4-2
Issue 2.2
sends the RF FAULT signal to the CPU if the 1ST LO
signal level falls below a preset level.
4-2.4.5
Second Mixer
. The second mixer section converts
the 1ST IF at 40.456 MHz, to the 2ND IF of 456 kHz. The
1ST IF signal enters the section and is applied to the 2nd
mixer. The 2ND IF at 456 kHz is produced by mixing the
1ST IF at 40.456 MHz with the 2ND LO frequency at 40.000
MHz. The signal is filtered, amplified, and applied to the
third mixer, and to the rear panel as the WBIF signal.
4-2.4.6
Second LO.
The second LO operates on a fixed
frequency of 40.000 MHz. This frequency is derived by
applying the 10 MHz reference signal to a pair of cascaded
bipolar transistor frequency doublers. The first doubler is
followed by a two-pole bandpass filter. The filter output
drives the second doubler followed by a four-pole
bandpass filter. The filter output is applied to the second
LO driver in the second mixer circuit.
4-2.4.7
Third Mixer
. The third mixer section converts the
2ND IF to the 3RD IF using the third LO signal. The 2ND
IF signal enters the section and is applied to the 3rd mixer.
The 3RD IF at 24 kHz is produced by mixing the 2ND IF at
456 kHz with the 3RD LO frequency at 480 kHz. The signal
is filtered and amplified before leaving the section.
4-2.4.8
Third LO.
The third LO circuit provides two fixed
frequencies. The circuit uses a 48 MHz VCO phase locked
to a 2 MHz reference (10 MHz ÷ 5) with a fixed loop divider
of 24. The VCO signal is split and applied to the
preselector for the BITE circuits, DSP circuits, and to a ÷100
circuit to generate the 480 kHz 3RD LO.
A fault detector sends the RF FAULT signal to the CPU if
the loop looses lock.
Overall voltage gain through the module is approximately
+72 dB.
4-2.5
Synthesizer Module.
The synthesizer module
provides the 1ST LO and 2ND/3RD LO frequencies used
for signal frequency conversion. It also contains the
reference frequency circuits for reference frequency
generation and switching, and audio circuits for audio
amplification and control.
Using the +8V, +17V, and -17V from the power supply,
three internal voltage regulators (not shown) supply the
required voltages to the entire module. These regulators
are mounted directly to the module surface for optimum
heat transfer.
4-2.5.1
Control.
The serial control DATA from the digital
module is clocked through a buffer into the fine
phase-locked loop (PLL) circuits and through a shift
register to the step PLL and audio circuits. At the proper
time, the DATA is latched into the PLL circuits by the
correct SYNTH ENABLE signal. The ENABLE signal also
latches the data into the shift register for the audio section.
The data latched into the PLL circuits is used to synthesize
the desired frequencies from the 10 MHz reference. Two
bits in the shift register select the correct audio source, and
enable or disable the speaker.
4-2.5.2
Reference Frequency.
The reference frequency
source is automatically selected by a detector that senses
the presence of an external reference signal. If the external
reference is detected, it is used as the basis for the
frequency generation. If the external reference is not
sensed, the internal oscillator (TCXO or optional OCXO) is
used for frequency generation. A potentiometer is used to
adjust the internal reference if necessary.
The 10 MHz external reference frequency may be daisy-
chained using the REF OUT connector on the rear panel.
If the signal is not daisy-chained, the REF IN signal may be
terminated if desired by connecting a 50 ohm load to the
REF OUT jack.
4-2.5.3
1st LO Generation.
The output loop circuits
produce the 1ST LO signal for the first mixer circuits using
the FINE LOOP and STEP LOOP inputs.
The frequency of the output loop VCO is controlled by
mixing the VCO output with the STEP LOOP frequency.
The resultant difference signal is frequency and phase
compared with the FINE LOOP frequency to produce the
output PLL DC control voltage.
The VCO output signal takes two paths. One path is
filtered and becomes the 1ST LO signal. The other path is
mixed with the STEP LOOP signal, producing a difference
frequency. The difference frequency is filtered through a
lowpass filter and applied to a phase/frequency detector
circuit.
The phase/frequency detector compares the difference
frequency with the FINE LOOP frequency and develops a
DC control voltage through a loop filter keeping the VCO
on frequency. A wrong-side frequency detector ensures
the output frequency locks only to the difference of the
STEP LOOP minus the VCO output frequency. If the VCO
frequency is higher than the step loop frequency, the
circuit disables the difference frequency which causes the
DC correction voltage to drive the VCO to a lower
frequency.
Courtesy of http://BlackRadios.terryo.org
