Service Manual Ponygraphic
Chapter 3
Part Description
3.3
3.1.
Pony graphic Unit
The Pony graphic Unit '96 version (P/N: C00307-0X-04), distributed since May 1996, is made
of 4 different PCBs:
Mother Board P/N: C01350-01-15
Display: P/N:
C01344-01-30
Keyboard: P/N:
C01352-01-15
Printer:
P/N: C01386-01-08
The physical structure of the Pony graphic Unit is described in the following block diagram:
The Unit contains most of the parts constituting the spirometer and can be interfaced to the, the
turbine flow meter and with the User's PC or external printer via the serial cable. AC/DC
adapter powers the unit.
3.2.
Mother Board (C01350-01-15)
3.2.1. Function
The Mother Board carries the components shown in the above diagram, all the connection
between them perform the following functions:
•
Control of the all peripherals (display, internal printer, keyboard...) through the micro
controller U1 (CDP6805);
•
Data Acquisition and amplification of the pulses coming from the opto electronic reader.
•
Serial communication management (RS232 unidirectional) and interface level regulation
through U11 (MAX233);
•
Battery voltage level detection;
•
Battery charging management through U10 (TEA1100) of Power Supply Board PCB.
The mother Board layout is enclosed in the Appendix.
3.2.2. Description
(1)
Micro controller (CPU) (U1)
The micro controller U1 (CDP6805E3) used in the Pony graphic is responsible for
Data management through its address bus for control data transfer function in accordance with
the firmware: stored in EPROM U4 (27C512 ,64KB)
(2) Clock
The frequency of the clock signal is controlled by the crystal X1 (4.194.304MHz) ,
Connected between pin 2 and pin 3 of the Real Timer Clock U2 (146818A).
The RTC (146818A) send the squared clock pulses to pin 39 of U1 (CPU) and generates the
interrupt signal necessary to measure the turbine pulses width (pin 19 of 146818A).
(3) I/O
control(U9)
The I/O control is carried out within the component FPGA (Field Programmable Gate Array) U9
(Actel A1010B). This IC compensates the Latches, Buffers, Logic Gates for control logic.
(4) Reset
The task of the Reset circuit is to boot the CPU program; when the reset signal (pin 1 of U1)
toggles from Low to High, the CPU executes the bootstrap program.
(5)
Power down (U13)
The Power Down circuit protects data stored in RAM in event of power failure. It disable the
RAM access by toggling pin 20 and 22 of the RAM U3 (62256). To logic level High
(6) RAM
(U3)
The IC (U3) 62256 is a 32KByte Random Access Memory used for saving the tests data and
for temporary memory during calculations. A dedicated circuit supplies power to the IC even if
the Pony graphic is switched off.
