6. RAS Functions
34
SCP-8550-LLV
Alarm out output control (4001h (bit5 - 7))
D7
D6
D5
D4
D3
D2
D1
D0
WD_S1 WD_S0 POS2_M
RESET
PIM2
PIM1
PIM0
R/W default: xxxx0000h
Figure 6.2.
Alarm out output control (4001h (bit5 - 7))
PO2_M: PO PO2/WDT pin output setting
0: Set the RAS connector's PO2/WDT (12) signal to PO2 (general-purpose output).
1: Set the RAS connector's PO2/WDT(12) signal to alarm out.
External alarm output status
WD_S1
WD_S0
When power is
turned off *1
When BIOS
starts *1
When
WDT starts
When time
expires on WDT
0
0
OFF
OFF
OFF
ON
1
0
OFF
OFF
ON
OFF
1
1
OFF
ON
ON
OFF
0
1
OFF
ON
OFF
ON
Figure 6.3.
PO2_M: PO PO2/WDT pin output setting
WDT control (4002h)
D7
D6
D5
D4
D3
D2
D1
D0
-
-
-
-
-
-
-
R/W
Figure 6.4.
WDT control (4002h)
It interrupts at the rise time or by RESET. The controls as below-mentioned register.
WDT_CONTROL port (4002h)
R: Cancels WDT stop/alarm.
Read data is undefined.
W: Start and clear the WDT
Write A5h to start and clear the WDT.
WDT counter port (4003h)
D7
D6
D5
D4
D3
D2
D1
D0
OUT
T7
T6
T5
T4
T3
T2
T1
T0
Figure 6.5.
WDT counter port (4003h)
W:Writes watchdog timer count data.
Write watchdog timer counter expiration time data.
1sec
→
01h
8sec
→
08h
15sec
→
0Fh
30sec
→
1Eh
Summary of Contents for SCP-8550-LLV
Page 7: ...vi SCP 8550 LLV...
Page 37: ...5 Jumper setting 30 SCP 8550 LLV...
Page 47: ...6 RAS Functions 40 SCP 8550 LLV...