6. About Hardware
64
DIG-100M1002-PCI
Delay time at the time of output
Output width at the time of output
Figure 6.4. Timing for External Samplicg Clock
Figure 6.5. Timing for External Trigger Input Signal
Table 6.2. Timing Table of External Control Signals
Parameter
Symbol Time (Unit)
Delay time from external trigger input signal until A/D conversion start pulse
*1.
t
DEC1
5nsec *2
Set up time of external trigger input signal (Rising edge)
t
SRS
10nsec
Hold time of external trigger input signal (Rising edge)
t
HRS
10nsec
Set up time of external trigger input signal (Falling edge)
t
SFS
10nsec
Hold time of external trigger input signal (Falling edge)
t
HRS
10nsec
Delay time until internal clock in output to external trigger output signal
t
OD
35nsec
Period when internal clock is maintained to "H" (When pulse output is set) *3
t
OP
50nsec
Period when internal clock is maintained to "H" (When pulse output is not set)
*3
t
OP
10nsec
*1 It is the delay time when internal clock is used.
When digital filter is being used, the delay time is added by 50ns.
*2 1nsec is 1/1,000,000,000 seconds.
*3 The internal clock less than 100nsec cannot be output.
And it is always maintained to “H”at 100nsec.
All the model values are shown at the time of Table 6.2.
Internalclk
TRG (Output)
used as internal clock output
t
OP
t
OD
CAUTION