4. Functions
62
CNT32-4MT(LPCI)
Abnormal input error
An abnormal input error occurs when the counter input signal changes on the A and B phases
simultaneously. Notification of the error is via a status (latch/clear), interrupt, or external output
(one-shot pulse). If the digital filter is enabled, an abnormal input error occurs when both the A and B
phases change during one period of the digital filter source clock. When the filter is disabled, an
abnormal input error occurs when both the A and B phases change during one period of the board 's
40MHz (25nsec) reference clock.
A possible cause of the abnormal input error is as follows.
-
When the phase difference between phases-A and B is shorter than one digital filter source clock
cycle (25 nsec with no filter set)
-
Noise is generated.
Phase-A input
Phase-B input
An abnormal input error is reported if phases-A and B
change in level during the filter source clock cycle.
No abnormal input error is reported when
the phase difference is longer than the
filter source clock cycle.
Filter source clock
Phase-A input
Phase-B input
Figure 4.17. Abnormal input error
