7. About Hardware
Control Signal Timings
Control Signal Timings for Analog Input
Figures 7.3, 7.4, 7.5, and Table 7.2 show the control signal timings for the analog input function.
t
DEC
External Smapling Clock Input
t
DEH
Conversion start
Sample / Hold
Figure 7.3. Timing Chart of External Sampling Clock
External Smapling Start Trigger Input
t
HRS
t
SRS
t
HFS
t
SFS
Figure 7.4. Timing Chart of Sampling Start Control Signal
External Smapling Stop Trigger Input
t
HRP
t
SRP
t
HFP
t
SFP
Figure 7.5. Timing Chart of Sampling Stop Control Signal
Table 7.2. Control Signal Timings
Parameter Symbol
Time
Unit
Delay from external sampling clock cycle to first channel hold
t
DEH
100 nsec
Delay from external sampling clock cycle to first channel A/D conversion start
pulse
t
DEC
100 nsec
Set up time of sampling start (Rising edge)
t
SRS
100 nsec
Hold time of sampling start (Rising edge)
t
HRS
100 nsec
Set up time of sampling start (Falling edge)
t
SFS
100 nsec
Hold time of sampling start (Falling edge)
t
HFS
100 nsec
Set up time of sampling stop (Rising edge)
t
SRP
100 nsec
Hold time of sampling stop (Rising edge)
t
HRP
100 nsec
Set up time of sampling stop (Falling edge)
t
SFP
100 nsec
Hold time of sampling stop (Falling edge)
t
HFP
100 nsec
CAUTION
The times listed in Table 7.2 are for standard operating conditions.
AIO-160802AY-USB
67
