Evaluation Kit User Manual
EV9000
2001 Consumer Microcircuits Limited
38
UM9000/2
4.6.5
Test 5: BER & DQ test 'B' to 'A' using unformatted data
4.6.5.1 Application
This test measures the received bit error rate of a continuous pseudorandom data stream without
using any of the formatting or error correction features which would normally be used for message
transfer. At the end of the test it reports the average BER and Data Quality readings. (Also see
Appendix B for further details on the CMX969 test).
4.6.5.2 Description
This test transmits a stream of pseudorandom data from channel B to channel A and calculates
the received bit error rate. The length of the stream is configured via the BER Test parameter and
a fixed length pseudorandom sequence is used (see Figure 22).
During the test, the Data Quality register is repeatedly read and its average result is reported,
providing an indication of the quality of the received signal, as analysed by the receiving modem.
Receive PLL (clock) and level acquisition functions are initiated once only, early in the test
sequence, but their execution is not timed for optimal (in terms of acquisition speed and quality)
acquisition performance. In order to obtain a high quality of both PLL and level acquisition, an
extended ‘1100..’ preamble is transmitted by the CMX909B software, or an extended sequence of
random data is transmitted by the CMX969, FX919B and FX929B software prior to the
pseudorandom data stream. The received bit error rate measurement uses a self-synchronising
algorithm, necessary because the transmitted data stream does not include any form of Frame
Synchronisation except for CMX969, FX919B and FX929B tests using the ‘Level Track’ LEVRES
setting, where Frame Synchronisation is sent early in the transmission to activate the AQLEV
sequence correctly.
4.6.5.3 Screen Controls
There are no windows dedicated to this test. Press the HALT switch to abort this test.
4.6.5.4 Test Sequence
The following sequence is performed upon starting the test. Channel B activity is shown in bold
lettering.
1.
Write channel A control register
2.
Write channel B control register
3.
IF chip type is CMX909B
4.
Write channel A mode register with:
set: IRQNEN, DQEN
clear: TX/RXN, PSAVE
5.
Write channel B mode register with:
set: IRQNEN, TX/RXN
clear:
PSAVE
6. ELSE
7.
Write channel A mode register with:
set: IRQNEN, RXEYE
clear: TX/RXN, PSAVE, SSIEN
8.
Write channel B mode register with:
set: IRQNEN, TX/RXN
clear: PSAVE, SSIEN
9.
Read channel A status register
10.
Read channel B status register
11.
Read channel A DQ register
12.
Read channel B DQ register
13.
Write RESET to channel A command register
14.
Write RESET to channel B command register