Connect One
II-EVB-365 SMT
User’s Manual
22
Appendix 4: SPI Host Interface
Introduction
The Nano WiReach/Socket iWiFi contains an SPI slave port, which allows a Host
processor to interface the iChip using an SPI Master port.
The SPI data transfer shall be based on the 'Command-Response' principle. (Half
Duplex). Meaning, until the HOST gets an answer to a command, it won't send a
new one.
Several assumptions have been made:
Number of bits per transfer is: 8.
No echo from the module to HOST (i.e. when module’s host interface is
set to SPI, the command AT+iEn is meaningless.
When module’s host interface is set to SPI, the module won't support
SerialNet mode since it is not Half Duplex compatible.
When module’s host interface is set to SPI, the module won't support the
―+++‖ Escape sequence.
The SPI interface will have the following behavior:
Fixed peripheral select
The CS is directly connected to the SPI Master device
Mode fault detection is enabled
The inactive state value of the serial clock is logic level zero
Data is changed on the leading edge of the serial clock and captured on the
following edge of the serial clock
The peripheral chip select line rises as soon as the last transfer is achieved
SPI Protocol
A module GPIO Output signal is dedicated as the SPI Control signal (nSPI_INT).
After receiving a command from the Host, the module will assert this signal for the
duration of its response. The Host should not attempt to send the next command until
this signal is de-asserted. The SPI control signal pin is defined with the new +iSPIP
parameter described below.
The SPI control signal is also utilized as a flow-control signal when the Host transmits
data to the module.
Data from module to Host (Slave to Master)
When the module replies to the Host commands it sends data packets preceded by a 2-
byte header using the following structure:
1
0
0
0
4bits MSB
8bits LSB
Bit 15 is the Data-Ready bit 12bits Data Length
