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2017

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Table 13 PCI Express Signal Descriptions (general purpose)

Signal

Pin # Description

I/O

PU/PD

Comment

P
PCIE_RX0-

B68
B69

PCI Express channel 0, Receive Input differential pair.

I PCIE

Supports PCI Express Base Specification, Revision 3.0

P
PCIE_TX0-

A68
A69

PCI Express channel 0, Transmit Output differential pair.

O PCIE

Supports PCI Express Base Specification, Revision 3.0

P
PCIE_RX1-

B64
B65

PCI Express channel 1, Receive Input differential pair.

I PCIE

Supports PCI Express Base Specification, Revision 3.0

P
PCIE_TX1-

A64
A65

PCI Express channel 1, Transmit Output differential pair.

O PCIE

Supports PCI Express Base Specification, Revision 3.0

P
PCIE_RX2-

B61
B62

PCI Express channel 2, Receive Input differential pair.

I PCIE

Supports PCI Express Base Specification, Revision 3.0

P
PCIE_TX2-

A61
A62

PCI Express channel 2, Transmit Output differential pair.

O PCIE

Supports PCI Express Base Specification, Revision 3.0

P
PCIE_RX3-

B58
B59

PCI Express channel 3, Receive Input differential pair.

I PCIE

Supports PCI Express Base Specification, Revision 3.0

P
PCIE_TX3-

A58
A59

PCI Express channel 3, Transmit Output differential pair.

O PCIE

Supports PCI Express Base Specification, Revision 3.0

P
PCIE_RX4-

B55
B56

PCI Express channel 4, Receive Input differential pair.

I PCIE

Supports PCI Express Base Specification, Revision 3.0

P
PCIE_TX4-

A55
A56

PCI Express channel 4, Transmit Output differential pair.

O PCIE

Supports PCI Express Base Specification, Revision 3.0

P
PCIE_RX5-

B52
B53

PCI Express channel 5, Receive Input differential pair.

I PCIE

Supports PCI Express Base Specification, Revision 3.0

P
PCIE_TX5-

A52
A53

PCI Express channel 5, Transmit Output differential pair.

O PCIE

Supports PCI Express Base Specification, Revision 3.0

PCIE_
PCIE_CLK_REF-

A88
A89

PCI Express Reference Clock output for all PCI Express
and PCI Express Graphics Lanes.

O PCIE

A PCI Express Gen2/3 compliant clock buffer chip must be used
on the carrier board if the design involves more than one PCI
Express device.

Note

PCIe lanes 4 and 5 are not supported if the optional PEG port is implemented.

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Summary of Contents for COM Express conga-TC175

Page 1: ...Copyright 2017 congatec AG TCKLm10 1 71 COM Express conga TC175 7th Generation Intel Core i7 i5 i3 and Celeron Single Chip Ultra Low TDP Processors User s Guide Revision 1 0 ...

Page 2: ... dd Author Changes 0 1 2017 02 10 AEM Preliminary release 1 0 2017 08 02 AEM Updated sections 2 5 Power Consumption and 2 6 Supply Voltage Battery Power Updated table 35 Connector C D Pinout Updated the note in section 6 1 2 6 Fan Control Updated section 10 BIOS Setup Description ...

Page 3: ...or indirectly from any technical or typographical errors or omissions contained herein or for discrepancies between the product and the user s guide In no event shall congatec AG be liable for any incidental consequential special or exemplary damages whether based on tort contract or otherwise arising out of or in connection with this user s guide or any other information contained herein or the u...

Page 4: ...ngatec AG All rights reserved All text pictures and graphics are protected by copyrights No copying is permitted without written permission from congatec AG congatec AG has made every attempt to ensure that the information in this document is accurate yet the information contained within is supplied as is Trademarks Product names logos brands and other trademarks featured or referred to within thi...

Page 5: ... non conforming product freight prepaid congatec AG will pay for transporting the repaired or exchanged product to the customer Repaired replaced or exchanged product will be warranted for the repair warranty period in effect as of the date the repaired exchanged or replaced product is shipped by congatec or the remainder of the original warranty whichever is longer This Limited Warranty extends t...

Page 6: ...hich have been made available to assist you If you still require assistance after visiting our website then contact our technical support department by email at support congatec com Terminology Term Description GB Gigabyte GHz Gigahertz kB Kilobyte MB Megabyte Mbit Megabit kHz Kilohertz MHz Megahertz TDP Thermal Design Power PCIe PCI Express SATA Serial ATA PEG PCI Express Graphics PCH Platform Co...

Page 7: ...Serial Interface 24 5 1 12 GPIOs 25 5 1 13 Power Control 25 5 1 14 Power Management 28 5 2 Secondary Connector Rows C and D 29 5 2 1 PCI Express 29 5 2 2 PCI Express Graphics PEG 29 5 2 3 Digital Display Interface 29 5 2 3 1 HDMI 30 5 2 3 2 DVI 30 5 2 3 3 DisplayPort DP 30 5 2 4 USB 3 0 31 6 Additional Features 32 6 1 eMMC 5 0 32 6 2 congatec Board Controller cBC 32 6 2 1 Board Information 32 6 2 ...

Page 8: ...esume Events 41 7 4 DDR4 Memory 41 8 Signal Descriptions and Pinout Tables 42 8 1 A B Connector Signal Descriptions 43 8 2 A B Connector Pinout 52 8 3 C D Connector Signal Descriptions 54 8 4 C D Connector Pinout 63 8 5 Boot Strap Signals 65 9 System Resources 66 9 1 I O Address Assignment 66 9 1 1 LPC Bus 66 9 2 PCI Configuration Space Map 67 9 3 I2 C 68 9 4 SM Bus 68 10 BIOS Setup Description 69...

Page 9: ...escriptions 47 Table 18 LVDS Signal Descriptions 47 Table 19 Embedded DisplayPort Signal Descriptions 48 Table 20 SPI BIOS Flash Interface Signal Descriptions 49 Table 21 Miscellaneous Signal Descriptions 49 Table 22 General Purpose I O Signal Descriptions 50 Table 23 Power and System Management Signal Descriptions 50 Table 24 General Purpose Serial Interface Signal Descriptions 51 Table 25 Power ...

Page 10: ...pinout definition and comply with COM Express 2 1 specification They are equipped with two high performance connectors that ensure stable data throughput The COM computer on module integrates all the core components and is mounted onto an application specific carrier board COM modules are legacy free design no Super I O PS 2 keyboard and mouse and provide most of the functional requirements for an...

Page 11: ...ide are available on your particular module Table 2 conga TC175 Variants Part No 045250 045251 045252 045253 Processor Intel Core i7 7600U 2 8 GHz Dual Core Intel Core i5 7300U 2 6 GHz Dual Core Intel Core i3 7100U 2 4 GHz Dual Core Intel Celeron 3965U 2 2 GHz Dual Core Intel Smart Cache 4 MByte 3 MByte 3 MByte 2 MByte Max Turbo Frequency 3 9 GHz 3 5 GHz N A N A Processor Graphics Intel HD Graphic...

Page 12: ...eo Technology HD hardware accelerated video decode encode processing transcode Switchable Hybrid graphics Up to 3 independent displays must be two DDI s DP HDMI DVI and one eDP LVDS 1x LVDS Up to 2x DDIs with support for 2x DisplayPort DisplayPort 1 2 2x HDMI 1 4a 1 or HDMI 2 0 1 2 2x DVI port 1 Resolutions up to 4K Optional Interface assembly options 1x eDP 1 4 1x VGA 3 NOTE 1 Requires an externa...

Page 13: ...ne what options are available on your particular module 2 2 Supported Operating Systems The conga TC175 supports the following operating systems Microsoft Windows 10 WindRiver VxWorks VX7 or later Linux Note The Intel Kaby Lake SoC supports only 64 bit operating systems 2 3 Mechanical Dimensions 95 0 mm x 95 0 mm Height approximately 18 or 21 mm including heatspreader depending on the carrier boar...

Page 14: ...lts Derated Input Volts Max Input Ripple 10Hz to 20MHz mV Max Module Input Power w derated input Watts Assumed Conversion Efficiency Max Load Power Watts VCC_12V 12 12 11 4 12 6 11 4 100 137 85 116 VCC_5V SBY 2 5 4 75 5 25 4 75 50 9 VCC_RTC 0 5 3 2 0 3 3 20 2 4 2 Rise Time The input voltages shall rise from 10 percent of nominal to 90 percent of nominal at a minimum slope of 250 V s The smooth tur...

Page 15: ...omment S0 Minimum value Lowest frequency mode LFM with minimum core voltage during desktop idle S0 Maximum value Highest frequency mode HFM Turbo Boost The CPU was stressed to its maximum frequency S0 Peak current Highest current spike during the measurement of S0 Maximum value This state shows the peak value during runtime Consider this value when designing the system s power supply to ensure tha...

Page 16: ... 0 05 045253 4 GB C 1 R004 Windows 10 Intel Celeron 3965U 2 2 2 N A 0 29 1 37 1 42 0 06 0 05 2 6 Supply Voltage Battery Power Table 6 CMOS Battery Power Consumption RTC Voltage Current 10o C 3V DC 1 48 µA 20o C 3V DC 1 63 µA 70o C 3V DC 2 31 µA Note 1 Do not use the CMOS battery power consumption values listed above to calculate CMOS battery lifetime 2 Measure the CMOS battery power consumption of...

Page 17: ...o 80 C Humidity Operation 10 to 90 Storage 5 to 95 Caution The above operating temperatures must be strictly adhered to at all times When using a congatec heatspreader the maximum operating temperature refers to any measurable spot on the heatspreader s surface Humidity specifications are for non condensing conditions ...

Page 18: ...3 PCIe 4 PCIe 5 PCIe 6 PCIe 9 PCIe 10 PCIe 11 X 2x SO DIMM X1 X2 SPI Flash 0 LVDS eDP assembly option TPM Mux LPC SDIO SATA 6G USB 2 0 SM Bus eMMC UART0 1 GPIOs Low Power Interconnect congatec System Management Controller Optional DP to VGA Ethernet 10 100 1000 Intel i219LM eDP to LVDS Bridge eMMC Flash 1 Note 1 Not supported by default assembly option 1 1 1 1 Ethernet VGA LVDS eDP COM Express Typ...

Page 19: ...olution CSP Heatspreader The dimensions of the cooling solutions are shown below and all measurements are in millimeters The mechanical system assembly mounting shall follow the valid DIN ISO specifications The maximum torque specification for all screws is 0 3 Nm Higher torque may damage the module and or carrier board 4 1 CSP Dimensions ...

Page 20: ...der is the thermal interface where most of the heat generated by the module is dissipated it is not to be considered as a heatsink It has been designed as a thermal interface between the module and the application specific thermal solution The application specific thermal solution may use heatsinks with fans and or heat pipes which can be attached to the heatspreader Some thermal solutions may als...

Page 21: ...ect operating temperature of the module is maintained at all times This may require additional cooling components for your final application s thermal solution For adequate heat dissipation use the mounting holes on the cooling solution to attach it to the module Apply thread locking fluid on the screws if the cooling solution is used in a high shock and or vibration environment To prevent the sta...

Page 22: ...ga TC175 offers three SATA interfaces SATA 0 2 on the A B connector The interfaces support independent DMA operation data transfer rates up to 6 0 Gb s AHCI mode using memory space and RAID mode Hot plug detect Note The interface does not support legacy mode using I O space 5 1 2 USB 2 0 The conga TC175 offers 8 USB 2 0 interfaces on the A B connector The xHCI host controller in the PCH supports t...

Page 23: ...the Intel 100 Series PCH LP For information about the decoded LPC addresses see section 9 1 1 5 1 6 I C Bus Fast Mode The I C bus is implemented through the congatec board controller Texas Instruments Tiva TM4E1231H6ZRB and accessed through the congatec CGOS driver and API The controller provides a fast mode multi master I C bus that has the maximum I C bandwidth 5 1 7 PCI Express The conga TC175 ...

Page 24: ...The LVDS interface supports single or dual channel LVDS color depths of 18 bpp or 24 bpp integrated flat panel interface with clock frequency up to 112 MHz VESA and OpenLDI LVDS color mappings automatic panel detection via Embedded Panel Interface based on VESA EDIDTM 1 3 resolution up to 1920x1200 in dual LVDS bus mode Note The LVDS eDP interface supports either LVDS or eDP signals Both signals a...

Page 25: ... can start its onboard power sequencing Carrier board hardware must drive this signal low until all power rails and clocks are stable Releasing PWR_OK too early or not driving it low at all can cause numerous boot up problems It is a good design practice to delay the PWR_OK signal a little typically 100ms after all carrier board power rails are up to ensure a stable system A sample screenshot is s...

Page 26: ...hardware drives the signal low until it is safe to let the module boot up When considering the above shown voltage divider circuitry and the transistor stage the voltage measured at the PWR_OK input pin may be only around 0 8V when the 12V is applied to the module Actively driving PWR_OK high is compliant to the COM Express specification but this can cause back driving Therefore congatec recommend...

Page 27: ... an operator wants to turn the power on or off The response to this signal from the system may vary as a result of modifications made in BIOS settings or by system software Standard 12V Power Supply Implementation Guidelines 12 volt input power is the sole operational power source for the conga TC175 The remaining necessary voltages are generated internally on the module using onboard voltage regu...

Page 28: ...x The Deep Sx is a lower power state employed to minimize the power consumption while in S3 S4 S5 In the Deep Sx state the system entry condition determines if the system context is maintained or not All power is shut off except for minimal logic which supports limited set of wake events for Deep Sx The Deep Sx on resumption puts system back into the state it is entered from In other words if Deep...

Page 29: ... VGA adapter IC This option requires a customized conga TC175 variant The conga TC175 supports up to three independent displays The display combination must be 2 DDI and 1 LVDS eDP For customized variants with optional VGA the combination must be 1x DDI Port B 1x VGA via Port C and 1x eDP The table below shows the conga TC175 display combination This table does not apply to customized variants equ...

Page 30: ...lay Interface of the COM Express connector Note The conga TC175 supports a maximum of two independent DVI displays Revisions equipped with optional VGA interface support only one DVI interface See table 2 above for possible display combinations 5 2 3 3 DisplayPort DP The conga TC175 offers two DP ports each capable of supporting data rate of 1 62 GT s 2 97 GT s and 5 4 GT s on 1 2 or 4 data lanes ...

Page 31: ...orts are controlled by the xHCI host controller provided by the Intel 100 Series PCH LP which is integrated in the Multi Chip Package The host controller allows data transfers of up to 5 Gb s and supports SuperSpeed High Speed Full Speed and Low Speed traffic Note The xHCI controller supports USB debug port on all USB 3 0 capable ports ...

Page 32: ...mongst all congatec modules The board controller supports the following features 6 2 1 Board Information The cBC provides a rich data set of manufacturing and board information such as serial number EAN number hardware and firmware revisions and so on It also keeps track of dynamically changing data like runtime meter and boot counter 6 2 2 Watchdog The conga TC175 is equipped with a multi stage w...

Page 33: ...trol using a PWM Pulse Width Modulation output Additionally there is an input signal called FAN_TACHOIN that provides the ability to monitor the system s fan RPMs revolutions per minute This signal must receive two pulses per revolution in order to produce an accurate reading For this reason a two pulse per revolution fan or similar hardware solution is recommended Note 1 A four wire fan must be u...

Page 34: ...d BIOS 6 3 3 OEM POST Logo This feature allows system designers to replace the congatec POST logo displayed in the upper left corner of the screen during BIOS POST with their own BIOS POST logo Use the congatec system utility CGUTIL 1 5 4 or later to replace add the OEM POST logo 6 3 4 OEM BIOS Code Data With the congatec embedded BIOS it is possible for system designers to add their own code to t...

Page 35: ...the following documents congatec Battery Management Interface Specification Battery System Design Guide conga SBM3 User s Guide 6 5 API Support CGOS In order to benefit from the above mentioned non industry standard feature set congatec provides an API that allows application software developers to easily integrate all these features into their code The CGOS API congatec Operating System Applicati...

Page 36: ...ice is treated as a master and a hardware assisted native command queuing AHCI also provides hot plug and advanced power management to improve usability 7 1 1 2 RAID The PCH LP supports RAID 0 1 and 5 on the 3 SATA ports Software components include an Option ROM and UEFI driver for pre boot configuration and boot functionality a Microsoft Windows compatible driver and a user interface for configur...

Page 37: ...ar intervals until the upper limit is met or the maximum possible upside for the number of active cores is reached For more information about Intel Turbo Boost 2 Technology visit the Intel website Note Only conga TC175 variants that feature the Core i7 and i5 processors support Intel Turbo Boost 2 Technology Refer to the power consumption tables in section 2 5 of this document for information abou...

Page 38: ...lly switch off the system it is necessary to use an ATX style power supply 7 2 3 Processor Performance Control Intel processors found on the conga TC175 run at different voltage frequency states performance states referred to as Enhanced Intel SpeedStep technology EIST Operating systems that support performance control take advantage of microprocessors that use several different performance states...

Page 39: ... do not need to be recompiled and may or may not benefit from the 64 bit extensions The application will likely need to be re certified by the vendor to run on the new 64 bit extended operating system 3 64 bit Mode 64 bit operating system and 64 bit applications This usage requires 64 bit device drivers It also requires applications to be modified for 64 bit operation and then recompiled and valid...

Page 40: ... does not offer virtual machine monitor VMM software All VMM software support questions and queries should be directed to the VMM software vendor and not congatec technical support 7 2 6 Thermal Management ACPI is responsible for allowing the operating system to play an important part in the system s thermal management This results in the operating system having the ability to take control of the ...

Page 41: ...nabled in the Power setup menu USB Mouse Keyboard Event When Standby mode is set to S3 USB hardware must be powered by standby power source Set USB Device Wakeup from S3 S4 to ENABLED in the ACPI setup menu if setup node is available in BIOS setup program In Device Manager look for the keyboard mouse devices Go to the Power Management tab and check Allow this device to bring the computer out of st...

Page 42: ...y the chip vendors only pull ups or pull downs implemented by congatec are listed For information about the internal pull ups or pull downs implemented by the chip vendors refer to the respective chip s datasheet Table 9 Terminology Descriptions Term Description PU congatec implemented pull up resistor PD congatec implemented pull down resistor I O 3 3V Bi directional signal 3 3V tolerant I O 5V B...

Page 43: ...udio Serial Data In 0 These signals are serial TDM data inputs from the three codecs The serial input is single pumped for a bit rate of 24 Mbps for Intel High Definition Audio I 3 3VSB Pin B28 HDA_SDIN2 is not connected Note Some signals have special functionality during the reset process They may bootstrap some basic important functions of the module For more information refer to section 8 5 of ...

Page 44: ...channel 0 Receive Input differential pair I SATA Supports Serial ATA specification Revision 3 0 SATA0_TX SATA0_TX A16 A17 Serial ATA channel 0 Transmit Output differential pair O SATA Supports Serial ATA specification Revision 3 0 SATA1_RX SATA1_RX B19 B20 Serial ATA channel 1 Receive Input differential pair I SATA Supports Serial ATA specification Revision 3 0 SATA1_TX SATA1_TX B16 B17 Serial ATA...

Page 45: ...E_RX3 PCIE_RX3 B58 B59 PCI Express channel 3 Receive Input differential pair I PCIE Supports PCI Express Base Specification Revision 3 0 PCIE_TX3 PCIE_TX3 A58 A59 PCI Express channel 3 Transmit Output differential pair O PCIE Supports PCI Express Base Specification Revision 3 0 PCIE_RX4 PCIE_RX4 B55 B56 PCI Express channel 4 Receive Input differential pair I PCIE Supports PCI Express Base Specific...

Page 46: ...I O USB 2 0 compliant Backwards compatible to USB 1 1 USB1 A45 USB Port 1 data or D I O USB 2 0 compliant Backwards compatible to USB 1 1 USB2 A43 USB Port 2 data or D I O USB 2 0 compliant Backwards compatible to USB 1 1 USB2 A42 USB Port 2 data or D I O USB 2 0 compliant Backwards compatible to USB 1 1 USB3 B43 USB Port 3 data or D I O USB 2 0 compliant Backwards compatible to USB 1 1 USB3 B42 U...

Page 47: ... on the module An open drain driver from a USB current monitor on the carrier board may drive this line low I 3 3VSB PU 10k 3 3VSB Do not pull this line high on the carrier board Table 17 CRT Signal Descriptions Signal Pin Description I O PU PD Comment VGA_RED B89 Red for monitor Analog DAC output designed to drive a 37 5 Ohm equivalent load O Analog PD 150R Optional VGA_GRN B91 Green for monitor ...

Page 48: ...ines used for flat panel detection and control O 3 3V PU 2k2 3 3V for LVDS support default LVDS_I2C_DAT A84 DDC lines used for flat panel detection and control I O 3 3V PU 2k2 3 3V for LVDS support default Table 19 Embedded DisplayPort Signal Descriptions Signal Pin Description I O PU PD Comment eDP_TX3 eDP_TX3 eDP_TX2 eDP_TX2 eDP_TX1 eDP_TX1 eDP_TX0 eDP_TX0 A81 A82 A71 A72 A73 A74 A75 A76 eDP dif...

Page 49: ...connect Table 21 Miscellaneous Signal Descriptions Signal Pin Description I O PU PD Comment I2C_CK B33 General purpose I C port clock output input I O 3 3V PU 2K2 3 3VSB I2C_DAT B34 General purpose I C port data I O line I O 3 3V PU 2K2 3 3VSB SPKR B32 Output for audio enunciator the speaker in PC AT systems O 3 3V SPEAKER is a boot strap signal see note below WDT B27 Output indicating that a watc...

Page 50: ... the COM Express connector by default Table 23 Power and System Management Signal Descriptions Signal Pin Description I O PU PD Comment PWRBTN B12 Power button to bring system out of S5 soft off active on falling edge I 3 3VSB PU 10k 3 3VSB SYS_RESET B49 Reset button input Active low input Edge triggered System will not be held in hardware reset while this input is kept low I 3 3VSB PU 10k 3 3VSB ...

Page 51: ... 3 3V PU 10k 3 3VSB SLEEP B103 Sleep button Used by the ACPI operating system to bring the system to sleep state or to wake it up again I OD 3 3V PU 10k 3 3VSB Table 24 General Purpose Serial Interface Signal Descriptions Signal Pin Description I O PU PD Comment SER0_TX A98 General purpose serial port transmitter O 3 3V SER1_TX A101 General purpose serial port transmitter O 3 3V SER0_RX A99 Genera...

Page 52: ...A17 SATA0_TX B17 SATA1_TX A72 eDP_TX2 LVDS_A0 B72 LVDS_B0 A18 SUS_S4 B18 SUS_STAT A73 eDP_TX1 LVDS_A1 B73 LVDS_B1 A19 SATA0_RX B19 SATA1_RX A74 eDP_TX1 LVDS_A1 B74 LVDS_B1 A20 SATA0_RX B20 SATA1_RX A75 eDP_TX0 LVDS_A2 B75 LVDS_B2 A21 GND FIXED B21 GND FIXED A76 eDP_TX0 LVDS_A2 B76 LVDS_B2 A22 SATA2_TX B22 SATA3_TX A77 eDP LVDS_VDD_EN B77 LVDS_B3 A23 SATA2_TX B23 SATA3_TX A78 LVDS_A3 B78 LVDS_B3 A2...

Page 53: ... A45 USB0 B45 USB1 A100 GND FIXED B100 GND FIXED A46 USB0 B46 USB1 A101 SER1_TX B101 FAN_PWMOUT A47 VCC_RTC B47 EXCD1_PERST A102 SER1_RX B102 FAN_TACHIN A48 EXCD0_PERST B48 EXCD1_CPPE A103 LID B103 SLEEP A49 EXCD0_CPPE B49 SYS_RESET A104 VCC_12V B104 VCC_12V A50 LPC_SERIRQ B50 CB_RESET A105 VCC_12V B105 VCC_12V A51 GND FIXED B51 GND FIXED A106 VCC_12V B106 VCC_12V A52 PCIE_TX5 B52 PCIE_RX5 A107 VC...

Page 54: ...signal differential pairs for the Superspeed USB data path I USB_SSRX0 C3 I USB_SSTX0 D4 Additional transmit signal differential pairs for the Superspeed USB data path O USB_SSTX0 D3 O USB_SSRX1 C7 Additional receive signal differential pairs for the Superspeed USB data path I USB_SSRX1 C6 I USB_SSTX1 D7 Additional transmit signal differential pairs for the Superspeed USB data path O USB_SSTX1 D6 ...

Page 55: ...PEG_RX9 PEG_RX10 PEG_RX10 PEG_RX11 PEG_RX11 PEG_RX12 PEG_RX12 PEG_RX13 PEG_RX13 PEG_RX14 PEG_RX14 PEG_RX15 PEG_RX15 C52 C53 C55 C56 C58 C59 C61 C62 C65 C66 C68 C69 C71 C72 C74 C75 C78 C79 C81 C82 C85 C86 C88 C89 C91 C92 C94 C95 C98 C99 C101 C102 PCI Express Graphics Receive Input differential pairs Note Can also be used as PCI Express Receive Input differential pairs 16 through 31 known as PCIE_RX...

Page 56: ...D88 D89 D91 D92 D94 D95 D98 D99 D101 D102 PCI Express Graphics Transmit Output differential pairs Note Can also be used as PCI Express Transmit Output differential pairs 16 through 31 known as PCIE_TX 16 31 and O PCIE Optional x1 or x2 PEG port requires re routing of PCIe lanes 5 and or 6 PEG_LANE_RV D54 PCI Express Graphics lane reversal input strap Pull low on the carrier board to reverse lane o...

Page 57: ...TA if DDI1_DDC_AUX_SEL is pulled high I O PCIE I O OD 3 3V PU 100k 3 3V DDI1_CTRLDATA_AUX is a boot strap signal see note below DDI enable strap already populated DDI1_DDC_AUX_SEL D34 Selects the function of DDI1_CTRLCLK_AUX and DDI1_CTRLDATA_AUX This pin shall have a IM pull down to logic ground on the module If this input is floating the AUX pair is used for the DP AUX signals If pulled high the...

Page 58: ...th DP3_AUX and HDMI3_CTRLCLK DP AUX function if DDI3_DDC_AUX_SEL is no connect HDMI DVI I2C CTRLCLK if DDI3_DDC_AUX_SEL is pulled high I O PCIE I O OD 3 3V Not supported DDI3_CTRLDATA_AUX C37 Multiplexed with DP3_AUX and HDMI3_CTRLDATA DP AUX function if DDI3_DDC_AUX_SEL is no connect HDMI DVI I2C CTRLDATA if DDI3_DDC_AUX_SEL is pulled high I O PCIE I O OD 3 3V Not supported DDI3_DDC_AUX_SEL C38 S...

Page 59: ...with DDI2_PAIR2 and DDI2_PAIR2 O PCIE TMDS2_DATA1 TMDS2_DATA1 D42 D43 HDMI DVI TMDS differential pair Multiplexed with DDI2_PAIR1 and DDI2_PAIR1 O PCIE TMDS2_DATA2 TMDS2_DATA2 D39 D40 HDMI DVI TMDS differential pair Multiplexed with DDI2_PAIR0 and DDI2_PAIR0 O PCIE HDMI2_HPD D44 HDMI DVI Hot plug detect Multiplexed with DDI2_HPD I PCIE PD 1M HDMI2_CTRLCLK C32 HDMI DVI I2 C Control Clock Multiplexe...

Page 60: ...ort of isochronous streams and secondary data Multiplexed with DDI1_PAIR0 and DDI1_PAIR0 O PCIE DP1_HPD C24 Detection of Hot Plug Unplug and notification of the link layer Multiplexed with DDI1_HPD I 3 3V PD 1M DP1_AUX D15 Half duplex bi directional AUX channel for services such as link configuration or maintenance and EDID access I O PCIE PD 100k DP1_AUX D16 Half duplex bi directional AUX channel...

Page 61: ...ondary data Multiplexed with DDI3_PAIR2 and DDI3_PAIR2 O PCIE Not supported DP3_LANE1 DP3_LANE1 C42 C43 Uni directional main link for the transport of isochronous streams and secondary data Multiplexed with DDI3_PAIR1 and DDI3_PAIR1 O PCIE Not supported DP3_LANE0 DP3_LANE0 C39 C40 Uni directional main link for the transport of isochronous streams and secondary data Multiplexed with DDI3_PAIR0 and ...

Page 62: ...rd logic may also implement a fault indicator such as an LED TYPE10 A97 Dual use pin Indicates to the carrier board that a Type 10 module is installed Indicates to the carrier that a Rev 1 0 2 0 module is installed PDS Not connected to indicate Pinout R2 0 TYPE10 NC PD 12V Pinout R2 0 Pinout Type 10 pull down to ground with 4 7k resistor Pinout R1 0 This pin is reclaimed from VCC_12V pool In R1 0 ...

Page 63: ...I1_PAIR6 D16 DDI1_CTRLDATA_AUX C71 PEG_RX6 D71 PEG_TX6 C17 RSVD D17 RSVD C72 PEG_RX6 D72 PEG_TX6 C18 RSVD D18 RSVD C73 GND D73 GND C19 PCIE_RX6 D19 PCIE_TX6 C74 PEG_RX7 D74 PEG_TX7 C20 PCIE_RX6 D20 PCIE_TX6 C75 PEG_RX7 D75 PEG_TX7 C21 GND FIXED D21 GND FIXED C76 GND D76 GND C22 PCIE_RX7 D22 PCIE_TX7 C77 RSVD D77 RSVD C23 PCIE_RX7 D23 PCIE_TX7 C78 PEG_RX8 D78 PEG_TX8 C24 DDI1_HPD D24 RSVD C79 PEG_R...

Page 64: ...9 PEG_RX14 D99 PEG_TX14 C45 RSVD D45 RSVD C100 GND FIXED D100 GND FIXED C46 DDI3_PAIR2 D46 DDI2_PAIR2 C101 PEG_RX15 D101 PEG_TX15 C47 DDI3_PAIR2 D47 DDI2_PAIR2 C102 PEG_RX15 D102 PEG_TX15 C48 RSVD D48 RSVD C103 GND D103 GND C49 DDI3_PAIR3 D49 DDI2_PAIR3 C104 VCC_12V D104 VCC_12V C50 DDI3_PAIR3 D50 DDI2_PAIR3 C105 VCC_12V D105 VCC_12V C51 GND FIXED D51 GND FIXED C106 VCC_12V D106 VCC_12V C52 PEG_RX...

Page 65: ... O PCIE I O OD 3 3V PU100k 3 3V DDI1_CTRLDATA_AUX is a boot strap signal see not below DDI2_CTRLDATA_AUX DP2_AUX HDM2_CTRLDATA C33 Multiplexed with DP2_AUX and HDMI2_CTRLDATA DP AUX function if DDI2_DDC_AUX_SEL is no connect HDMI DVI I2C CTRLDATA if DDI2_DDC_AUX_SEL is pulled high I O PCIE I O OD 3 3V PU100k 3 3V DDI2_CTRLDATA_AUX is a boot strap signal see not below Caution The signals listed in ...

Page 66: ... O cycles that are not positively decoded are forwarded to the PCI Bus not the LPC Bus Only specified I O ranges are forwarded to the LPC Bus In the congatec Embedded BIOS the following I O address ranges are sent to the LPC Bus 2Eh 2Fh 4Eh 4Fh 60h 64h A00h A1Fh E00h EFFh always used internally Parts of these ranges are not available if a Super I O is used on the carrier board If a Super I O is no...

Page 67: ...ME Interface 3 00h 17h 00h SATA Controller 00h Note2 1Ch 00h PCI Express Root Port 0 00h Note2 1Ch 01h PCI Express Root Port 1 00h Note2 1Ch 02h PCI Express Root Port 2 00h Note2 1Ch 03h PCI Express Root Port 3 00h Note2 1Ch 04h PCI Express Root Port 4 00h Note2 1Ch 05h PCI Express Root Port 5 00h Note2 1Dh 00h PCI Express Root Port 6 00h Note2 1Dh 02h PCI Express Root Port 7 00h 1Fh 00h PCI to LP...

Page 68: ...able represents a case when a single functional PCI PCIe device is connected to all possible slots on the carrier board The given bus numbers will change based on actual hardware configuration 4 Internal PCI devices not connected to the conga TC175 are not listed 9 3 I2 C Onboard resources are not connected to the I C bus Address 16h is reserved for congatec Battery Management solutions 9 4 SM Bus...

Page 69: ... BIOS for conga TC175 is identified as BVKLR1xx or BUKLR1xx where R is the identifier for a BIOS ROM file 1 is the so called feature number and xx is the major and minor revision number The BVKL binary size is 16 MB and the BUKL binary size is 8 MB 10 3 Updating the BIOS OEMs often use BIOS updates to correct platform issues discovered after the board has been shipped or when new features are adde...

Page 70: ...lash devices Winbond W25Q128FVSIG 16 MB Winbond W25Q64CVSSIG 8 MB The flash devices listed above can be used on the carrier board to support external BIOS For more information about external BIOS support refer to the Application Note AN7_External_BIOS_Update pdf on the congatec website at http www congatec com ...

Page 71: ...el com design chipsets industry lpc htm Universal Serial Bus USB Specification Revision 2 0 http www usb org home PCI Specification Revision 2 3 http www pcisig com specifications Serial ATA Specification Revision 3 0 http www serialata org PICMG COM Express Module Base Specification http www picmg org PCI Express Base Specification Revision 2 0 http www pcisig com specifications ...

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