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SA70m01
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Table 14.2
Optional MIPI-DSI Signal Description
Signals
Pins
Description
I/O
PU/PD Comments
DSI0_D0-
S125
S126
DSI0 primary differential data pair 0
O LVDS
D-PHY
Not supported by default
DSI0_D1-
S128
S129
DSI0 primary differential data pair 1
O LVDS
D-PHY
DSI0_D2-
S131
S132
DSI0 primary differential data pair 2
O LVDS
D-PHY
DSI0_D3-
S137
S138
DSI0 primary differential data pair 3
O LVDS
D-PHY
D
DSI0_CLK-
S134
S135
DSI0 primary differential clock pair
O LVDS
D-PHY
DSI0_TE
S144
DSI0 primary panel tearing effect signal
I 1.8V
LCD0_VDD_EN
S133
Primary panel power enable. High enables panel VDD
O 1.8V
LCD0_BKLT_EN
S127
Primary panel backlight enable. High enables panel backlight
O 1.8V
LCD0_BKLT_PWM
S141
Primary panel backlight brightness control via pulse width modulation (PWM)
O 1.8V
DSI1_D0-
S111
S112
DSI1 secondary differential data pair 0
O LVDS
D-PHY
DSI1_D1-
S114
S115
DSI1 secondary differential data pair 1
O LVDS
D-PHY
DSI1_D2-
S117
S118
DSI1 secondary differential data pair 2
O LVDS
D-PHY
DSI1_D3-
S120
S121
DSI1 secondary differential data pair 3
O LVDS
D-PHY
D
DSI1_CLK-
S108
S109
DSI1 secondary differential clock pair
O LVDS
D-PHY
LCD1_VDD_EN
S116
Secondary panel power enable. High enables panel VDD
O 1.8V
LCD1_BKLT_EN
S107
Secondary panel backlight enable. High enables panel backlight
O 1.8V
LCD1_BKLT_PWM
S122
Secondary panel backlight brightness via pulse width modulation (PWM)
O 1.8V
DSI1_TE
S113
DSI1 secondary panel tearing effect signal
I 1.8V
I2C_LCD_DAT
S140
DDC data line for flat panel detection and control. Possible EDID EEPROM
address conflicts may occur if multiple displays are implemented
I/O OD
1.8V
PU 2k2
I2C_LCD_CK
S139
DC clock line for flat panel detection and control
O 1.8V
PU 2k2
Note
The MIPI-DSI interface is not supported by default (assembly option only).
