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Congatec 048000, User Manual

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Congatec 048000 User Manual Download Page 44

Copyright 

© 

2017 

congatec 

AG 

 

      MA50m17 

       

44/60

Gigabit Ethernet Pin # Description

I/O

PU/PD Comment

GBE0_CTREF 

A14

Reference voltage for Carrier Board Ethernet channel 0 magnetics center tap. The reference voltage is 
determined by the requirements of the module PHY and may be as low as 0V and as high as 3.3V. The 
reference voltage output shall be current limited on the module. In the case in which the reference is 
shorted to ground, the current shall be limited to 250mA or less. 

Not connected

Table 17  

Serial ATA Signal Descriptions

Signal

Pin # Description

I/O

PU/PD Comment

S 
SATA0_RX-

A19
A20

Serial ATA channel 0, Receive Input differential pair.

I SATA

Supports Serial ATA specification, Revision 3.1

S 
SATA0_TX-

A16
A17

Serial ATA channel 0, Transmit Output differential pair.

O SATA

Supports Serial ATA specification, Revision 3.1

S 
SATA1_RX-

B19
B20

Serial ATA channel 1, Receive Input differential pair.

I SATA

Supports Serial ATA specification, Revision 3.1

S 
SATA1_TX-

B16
B17

Serial ATA channel 1, Transmit Output differential pair.

O SATA

Supports Serial ATA specification, Revision 3.1

S_ATA_ACT#

A28

Serial ATA activity indicator, active low.

O 3.3V

Up to 10mA

Table 18  

PCI Express Signal Descriptions (general purpose)

Signal

Pin # Description

I/O

PU/PD Comment

P 
PCIE_RX0-

B68
B69

PCI Express channel 0, Receive Input differential pair.

I PCIE

Supports PCI Express Base Specification, Revision 2.0

P 
PCIE_TX0-

A68
A69

PCI Express channel 0, Transmit Output differential pair. O PCIE

Supports PCI Express Base Specification, Revision 2.0

P 
PCIE_RX1-

B64
B65

PCI Express channel 1, Receive Input differential pair.

I PCIE

Supports PCI Express Base Specification, Revision 2.0

P 
PCIE_TX1-

A64
A65

PCI Express channel 1, Transmit Output differential pair. O PCIE

Supports PCI Express Base Specification, Revision 2.0

P 
PCIE_RX2-

B61
B62

PCI Express channel 2, Receive Input differential pair.

I PCIE

Supports PCI Express Base Specification, Revision 2.0

P 
PCIE_TX2-

A61
A62

PCI Express channel 2, Transmit Output differential pair. O PCIE

Supports PCI Express Base Specification, Revision 2.0

P 
PCIE_RX3-

B58
B59

PCI Express channel 3, Receive Input differential pair.

I PCIE

Supports PCI Express Base Specification, Revision 2.0

P 
PCIE_TX3-

A58
A59

PCI Express channel 3, Transmit Output differential pair. O PCIE

Supports PCI Express Base Specification, Revision 2.0

PCIE_ 
PCIE_CLK_REF-

A88
A89

PCI Express Reference Clock output for all PCI Express 
lanes.

O PCIE

A PCI Express Gen2/3 compliant clock buffer chip must be used on 
the carrier board if more than one PCI Express device is designed in.

Summary of Contents for 048000

Page 1: ...COM Express conga MA5 COM Express Type 10 Mini module based on the Intel Atom Pentium and Celeron Apollo Lake SoC User s Guide Revision 1 7...

Page 2: ...Electrostatic Sensitive Device information on page 3 Updated security features in table 4 Feature Summary Removed Android from supported OS in section 2 2 Supported Operating Systems Added EFT cautio...

Page 3: ...sumes no liability for any damages incurred directly or indirectly from any technical or typographical errors or omissions contained herein or for discrepancies between the product and the user s guid...

Page 4: ...that should be observed Copyright Notice Copyright 2017 congatec AG All rights reserved All text pictures and graphics are protected by copyrights No copying is permitted without written permission f...

Page 5: ...non conforming product freight prepaid congatec AG will pay for transporting the repaired or exchanged product to the customer Repaired replaced or exchanged product will be warranted for the repair w...

Page 6: ...equire assistance after visiting our website then contact our technical support department by email at support congatec com Terminology Term Description GB Gigabyte GHz Gigahertz kB Kilobyte MB Megaby...

Page 7: ...3 DVI D 27 5 7 4 LVDS eDP 28 5 8 SD Card 28 5 9 General Purpose Serial Interface UART 28 5 10 LPC Bus 29 5 11 SPI Bus 29 5 12 I C Bus 29 5 13 SMBus 29 5 14 Power Control 29 5 15 Power Management 31 5...

Page 8: ...criptions 43 9 System Resources 54 9 1 I O Address Assignment 54 9 1 1 LPC Bus 54 9 2 PCI Configuration Space Map 55 9 3 I C Bus 56 9 4 SM Bus 56 9 5 congatec System Sensors 57 10 BIOS Setup Descripti...

Page 9: ...eral purpose 44 Table 19 ExpressCard Support Pins Signal Descriptions 45 Table 20 USB Signal Descriptions 45 Table 21 LVDS Signal Descriptions 46 Table 22 LPC Signal Descriptions 47 Table 23 SPI Inter...

Page 10: ...pecific carrier board COM modules are legacy free design no Super I O PS 2 keyboard and mouse and provide most of the functional requirements for any application These functions include but are not li...

Page 11: ...24 bpp Single Channel LVDS 18 24 bpp Single Channel LVDS 18 24 bpp Single Channel LVDS 18 24 bpp Single Channel LVDS 18 24 bpp DDI Dual mode DP 1 2 HDMI 1 4b DVI Dual mode DP 1 2 HDMI 1 4b DVI Dual m...

Page 12: ...external level shifter on the carrier board Peripheral Interfaces 2x SATA 6 Gb s Up to 4x PCI Express Gen2 x1 links without LAN requires custom BIOS 6x USB 2 0 and 2x USB 3 0 2 0 SD MMC not supported...

Page 13: ...ge capacity of 20 GB congatec will not offer technical support for systems with less than 20 GB storage space 2 3 Mechanical Dimensions 84 0mm x 55 0mm Height approximately 18 or 21mm including heatsp...

Page 14: ...Input V Input Range V Derated Input V Max Input Ripple 10Hz to 20MHz mV Max Module Input Power w derated input W Assumed Conversion Efficiency Max Load Power W Wide Input 6 4 75 20 0 4 75 100 28 85 23...

Page 15: ...ment S0 Minimum value Lowest frequency mode LFM with minimum core voltage during desktop idle S0 Maximum value Highest frequency mode HFM Turbo Boost The CPU was stressed to its maximum frequency S0 P...

Page 16: ...02 2 GB A 1 M50R019 Windows 10 Intel Atom x5 E3930 2 1 3 1 8 0 12 0 88 0 94 0 12 0 10 048020 8 GB A 1 M50R019 Windows 10 Intel Pentium N4200 4 1 1 2 5 0 14 1 02 1 95 0 11 0 10 048022 4 GB A 1 M50R019...

Page 17: ...9_RTC_Battery_Lifetime pdf on congatec AG website at www congatec com support application notes 4 We recommend to always have a CMOS battery present when operating the conga MA5 2 7 Environmental Spec...

Page 18: ...T SPI INTEGRATED I O PCIe1 PCIe2 PCIe4 GBE PCIe0 SDv3 eMMC HS400 MIPI CSI x2 MIPI CSI x4 LPC SSD MIPI CSI2 on module DDR3L 2 4 8GB BIOS TPM PCIe GBE Intel i210 i211 MUX eDP LVDS 0R0 PCIe3 Support max...

Page 19: ...of 0 4 Nm for carrier board mounting screws 2 The gap pad material used on congatec heatspreaders may contain silicon oil that can seep out over time depending on the environmental conditions it is s...

Page 20: ...opyright 2017 congatec AG MA50m17 20 60 4 1 CSP Dimensions For Lidded Variants 25 21 4 55 84 M2 5 x 6 mm threaded standoff for threaded version or 2 7 x 6 mm non threaded standoff for borehole version...

Page 21: ...Copyright 2017 congatec AG MA50m17 21 60 For Bare die Variants 25 21 4 55 84 M2 5 x 6 mm threaded standoff for threaded version or 2 7 x 6 mm non threaded standoff for borehole version...

Page 22: ...ight 2017 congatec AG MA50m17 22 60 4 2 Heatpsreader Dimensions For Lidded Variants 7 9 11 55 84 M2 5 x 6 mm threaded standoff for threaded version or 2 7 x 6 mm non threaded standoff for borehole ver...

Page 23: ...Copyright 2017 congatec AG MA50m17 23 60 For Bare die Variants 7 9 11 55 84 M2 5 x 6 mm threaded standoff for threaded version or 2 7 x 6 mm non threaded standoff for borehole version...

Page 24: ...2 5 Gb s and Gen 2 5 Gb s speed For more information refer to the conga MA5 pinout table in section 8 Signal Descriptions and Pinout Tables and table 16 PCI Express Signal Descriptions Table 10 PCI E...

Page 25: ...m the SoC One USB 2 0 port supports Dual Role 5 4 1 USB 2 0 The conga MA5 offers six USB 2 0 interfaces on the COM Express connector including one USB 2 0 Dual Role port The xHCI host controller in th...

Page 26: ...press connector The DDI0 supports DP or HDMI DVI and the Local Flat Panel interface supports LVDS by default via an eDP to LVDS bridge IC or eDP as an assembly option Two independent displays are supp...

Page 27: ...ompact audio video connector interface for transmitting uncompressed digital streams HDMI encodes the video data into TMDS for digital transmission and is backward compatible with the single link Digi...

Page 28: ...840x2160 60Hz assembly option For more information contact congatec technical support Note The LVDS eDP interface supports either LVDS or eDP signals Both signals are not supported simultaneously See...

Page 29: ...is 25 MHz 5 12 I C Bus The I C bus is implemented through the congatec board controller The bus has 2 2k ohm pull ups resistors on the CLK and DATA signals and is powered from standby 3 3V 5 13 SMBus...

Page 30: ...to the power good signal of an ATX type power supply Connect PWR_OK to the last voltage regulator in the chain on the carrier board Simply pull PWR_OK with a 1k resistor to the carrier board 3 3V powe...

Page 31: ...oticed that on some occasions problems occur when using a power supply that produces non monotonic voltage when powered up The problem is that some internal circuits on the module e g clock generator...

Page 32: ...3 Fully slide the flat foil cable inside the slot below the actuator The exposed conductive traces of the flat foil cable must face up 4 Gently press against both sides of the actuator from above unt...

Page 33: ...from the x86 core architecture which results in higher embedded feature performance and more reliability even when the x86 processor is in a low power mode 6 2 1 Board Information The cBC provides a r...

Page 34: ...iplexed with SD signals and are controlled by the cBC 6 3 OEM BIOS Customization The conga MA5 is equipped with congatec Embedded BIOS which is based on American Megatrends Inc Aptio UEFI firmware The...

Page 35: ...ure can also be used to support Win XP SLP installation Window 7 SLIC table OA2 0 Windows 8 OEM activation OA3 0 verb tables for HDA codecs PCI PCIe opROMs bootloaders rare graphic modes and Super I O...

Page 36: ...these features into their code The CGOS API congatec Operating System Application Programming Interface is the congatec proprietary API that is available for all commonly used Operating Systems such a...

Page 37: ...tep Technology Intel 64 bit Architecture Intel full virtualization architecture supports Intel VT x with Extended Page Tables EPT Intel Virtualization Technology for Directed I O VT d Thermal manageme...

Page 38: ...en the temperature in the thermal zone must be reduced the operating system can decrease the power consumption of the processor by throttling the processor clock One of the advantages of this cooling...

Page 39: ...Device driver must be configured for Wake On LAN support PCI Express WAKE Wakes unconditionally from S3 S5 PME Activate the wake up capabilities of a PCI device using Windows Device Manager configura...

Page 40: ...nternal pull ups or pull downs implemented by the chip vendors only pull ups or pull downs implemented by congatec are listed For information about the internal pull ups or pull downs implemented by t...

Page 41: ...7 SATA0_TX B17 SATA1_TX A72 eDP_TX2 LVDS_A0 B72 DDI0_PAIR0 A18 SUS_S4 B18 SUS_STAT A73 eDP_TX1 LVDS_A1 B73 DDI0_PAIR1 A19 SATA0_RX B19 SATA1_RX A74 eDP_TX1 LVDS_A1 B74 DDI0_PAIR1 A20 SATA0_RX B20 SATA...

Page 42: ...S_RESET A104 VCC_12V B104 VCC_12V A50 LPC_SERIRQ B50 CB_RESET A105 VCC_12V B105 VCC_12V A51 GND FIXED B51 GND FIXED A106 VCC_12V B106 VCC_12V A52 RSVD B52 RSVD A107 VCC_12V B107 VCC_12V A53 RSVD B53 R...

Page 43: ...supported HDA_SDIN 2 1 are not connected Note On Intel Apollo Lake SoC the signals marked with asterisks have native voltage levels that are different from the levels defined in the COM Express Specif...

Page 44: ...neral purpose Signal Pin Description I O PU PD Comment PCIE_RX0 PCIE_RX0 B68 B69 PCI Express channel 0 Receive Input differential pair I PCIE Supports PCI Express Base Specification Revision 2 0 PCIE_...

Page 45: ...6 USB Port 7 differential data pairs I O USB 2 0 compliant Backwards compatible to USB 1 1 USB7_HOST_PRSNT B96 Module USB client may detect the presence of a USB host on USB7 A high value indicates th...

Page 46: ...Assembly option eDP LVDS_A2 eDP_TX0 A75 LVDS Channel A differential pair 2 Embedded Display Port channel 0 differential pair 0 O LVDS O eDP LVDS default Assembly option eDP LVDS_A2 eDP_TX0 A76 LVDS C...

Page 47: ...from module to carrier board SPI BIOS flash O 3 3VSB PD 100k SPI_POWER A91 Power source for carrier board SPI BIOS flash SPI_POWER shall be used to power SPI BIOS flash on the carrier only 3 3VSB BIOS...

Page 48: ...e function of DDI0_CTRLCLK_AUX and DDI0_CTRLDATA_ AUX This pin shall have a IM pull down to logic ground on the module If this input is floating the AUX pair is used for the DP AUX signals If pulled h...

Page 49: ...I interface implement an external level translator shifter e g PTN3360D on the carrier board Table 27 General Purpose Serial Interface Signal Descriptions Signal Pin Description I O PU PD Comment SER0...

Page 50: ...w SYS_RESET input a low PWR_OK input a main power input VIN that falls below the minimum specification a watchdog timeout or may be initiated by the module software O 3 3VSB PWR_OK B24 Power OK from m...

Page 51: ...Signal Pin Description I O PU PD Comment GPI0 A54 General purpose input pins Pulled high internally on the module Shared with SD_DATA0 Bidirectional signal I 3 3V PU 10K 3 3V GPI1 A63 General purpose...

Page 52: ...s to GPI1 IO 3 3V PU 20k SDIO_DAT2 A67 SDIO Data line Operates in push pull mode and maps to GPI2 IO 3 3V PU 20k SDIO_DAT3 A85 SDIO Data line Operates in push pull mode and maps to GPI3 IO 3 3V PU 20k...

Page 53: ...nal Pin Description I O PU PD Comment CAN0_TX A101 Controller Area Network TX output for CAN Bus channel 0 This pin is shared with SER1_TX O 3 3V Not supported CAN0_RX A102 Controller Area Network RX...

Page 54: ...Motherboard resources 0CF8h 0CFBh 4 bytes No PCI configuration address register 0CFCh 0CFFh 4 bytes No PCI configuration data register 0D00h F000h See note PCI PCI Express bus Note The BIOS assigns P...

Page 55: ...CI Configuration Space Map Bus Number hex Device Number hex Function Number hex Device ID Description and Device ID 00h 00h 00h 0x5AF0 Host Bridge 00h 02h 00h 0x5A84 Graphics and Display 00h 0Dh 00h 0...

Page 56: ...bove table represents a case when a single function PCI Express device is connected to all possible slots on the carrier board The given bus numbers will change based on actual hardware configuration...

Page 57: ...accessible through CGOS interface and also visible on the health monitor submenu in BIOS setup Two temperature sensors CPU temperature based on CPU digital thermal sensor Board temperature sensor loc...

Page 58: ...u do not have access to the restricted area of the congatec website contact your local congatec sales representative 10 1 Navigating the BIOS Setup Menu The BIOS setup menu shows the features and opti...

Page 59: ...user s guide for the congatec System Utility CGUTLm1x pdf on the congatec website at www congatec com Note 1 Deprecated Caution The DOS command line tool is not officially supported by congatec and t...

Page 60: ...cation Revision 1 0 LPC www intel com Universal Serial Bus USB Specification Revision 2 0 www usb org PCI Specification Revision 2 3 www pcisig com specifications Serial ATA Specification Revision 3 0...

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