Conexant Fusion 878A, Manual

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2.0 Functional Description
Fusion 878A
2.4 Video Scaling, Cropping, and Temporal Decimation PCI Video Decoder
2-18
Conexant
100600B
2.4.2.1 Cropping
Registers
Horizontal Delay
Register (HDELAY)
For video decoding, HDELAY is programmed with the number of pixels between
horizontal sync and the first pixel of each line to be displayed or captured. For
GPIO SPIOUT, the HDELAY is programmed with the number of pixels between
the falling edge of HRESET and the rising edge of HACTIVE. HDELAY should
be an even number to get Cb as the first pixel, an odd number to get Cr.
The register value is programmed with respect to the scaled frequency clock.
Horizontal Active
Register (HACTIVE)
For video decoding, HACTIVE is programmed with the actual number of
displayed or captured pixels per line. For GPIO SPIOUT, HACTIVE is
programmed with the number of pixels that HACTIVE signal is high after the
HACTIVE signal goes high.
The register value is programmed with respect to the scaled frequency clock.
The video line can be considered a combination of three components:
1.
Back porch and Sync: defined by HDELAY
2.
Active Video: defined by HACTIVE
3.
Front Porch: total scaled pixels—HDELAY through HACTIVE
For uncropped images, the square pixel values for these components at 4 × Fsc
are displayed in Table 2-4 .
Therefore, for uncropped images the values are:
For cropped images, HDELAY can be increased and HACTIVE decreased so
that HACTIVE
≤
889 × HSCALE for NTSC and
≤
1108 × HSCALE
for PAL. If HACTIVE is too much, then you will see front or back
porch pixels. Regions of the video signal are illustrated in
Table 2-13 .
Table 2-4. Square Pixel Values
Video
Standard
CLK x 1
Front Porch
CLK x 1 HDELAY CLK x 1 HACTIVE
CLK x 1
Total
NTSC 21 135 754 910
PAL/SECAM 27 186 922 1135
HDELAY (NTSC) = (135/754 × HACTIVE) & 0x3FE
HDELAY(PAL)
= (186/922 × HACTIVE) & 0x3FE
Figure 2-13. Regions of the Video Signal
HDELAY HACTIVE
Front
Porch
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