8
5 = internal generation of null test
sequence.
8-bit parallel input bytes are
transmitted MSb first.
Test sequences override external
input bit stream.
REG6(3:0)
BCH encoder
bypass
‘0’ = BCH encoder enabled
‘1’ = BCH encoder bypassed
REG6(4)
Signal gain
Signal level.
16-bit unsigned integer.
The maximum level should be
adjusted to prevent saturation. The
settings may vary slightly with the
selected symbol rate. Therefore, we
recommend checking for saturation
at the D/A converter when changing
either the symbol rate or the signal
gain.
REG7 = bits 7-0 (LSB)
REG8= bits 15-8 (MSB)
Transmit packet
size
N
pltx
Transmit packet size expressed in
number of payload symbols
N
pltx
.
Must be an integer of 8.
REG10: LSB
REG11(3:0): MSb
Transmission
window start
time
Start time of the window during
which the modulator is allowed to
initiate a frame transmission.
In
µ
s after the start of superframe.
Always zero for master unit.
REG12: LSB
REG13
REG14: MSB
Transmission
window end time
End time of the window during
which the modulator is allowed to
initiate a frame transmission. A
frame transmission in progress can
extend beyond the end of the
transmission window.
In us after the start of superframe.
REG15: LSB
REG16
REG17: MSB
Preamble
extension
Prepend a dummy preamble to the
packet to give the receiver AGC time
to converge before the sync field.
Expressed as number of symbols/8.
Valid range 0 – 255 (representing 0
to 2040 symbol preamble).
Adjust as a function of the receiver
AGC response time.
REG18
Output selection
The output selection is based on the
firmware option (i.e. personality)
loaded in the FPGA.
The modulator output can be
directed to one of several possible
interfaces:
(-A)
Digital 16-bit precision
unsigned, right (J9) connector,
compatible with COM-3504
(-B)
Digital 10-bit precision
unsigned, right (J9) connector,
compatible with COM-2001
(-C)
Digital 14-bit precision
unsigned, right (J9) connector,
compatible with COM-4004
A digital 1-bit precision output is
always present on left connector pin
B36 (valid only for OOK
modulation).
Click on the swiss army knife button
to select the proper firmware option.
Multi-Node Network Configuration
Mode
0 = Slave / remote unit
1 = Master / base station (one per
network)
REG11(7)
Half/Full Duplex
0 = Half-duplex. Tx/Rx are mutually
exclusive
1 = Full duplex. Tx/Rx can occur
simultaneously
REG11(6)
Superframe
period
Periodic superframe duration, in us.
REG20: LSB
REG21
REG22: MSB
Demodulator
Parameters
Configuration
Processing clock
f
clk_rx
Demodulator processing nominal
frequency.
The demodulator processing clock
also serves as ADC sampling clock.