ComBlock COM-1503, Manual, Page: 7 / 22

7
Configuration (Advanced)
Alternatively, users can access the full set of
configuration features by specifying 8-bit control
registers as listed below. These control registers can
be set manually through the ComBlock Control
Center or by software using the ComBlock API (see
www.comblock.com/download/M&C_reference.pdf
)
All control registers are read/write.
Definitions for the
Control registers and Status
registers are provided below.
Control Registers
The module configuration parameters are stored in
volatile (SRT command) or non-volatile memory
(SRG command). All control registers are
read/write.
Undefined control registers or register bits are for
backward software compatibility and/or future use.
They are ignored in the current firmware version.
Modulator
Parameters Configuration
Processing clock
f
clk_tx
Modulator processing clock.
Also serves as DAC sampling
clock after frequency doubling.
20-bit unsigned integer
expressed as
f
clk_tx
* 2
20
/
360MHz.
120 MHz maximum.
20 MHz recommended
minimum
REG0 = bits 7-0 (LSB)
REG1 = bits 15 – 8 (MSB)
REG2(3:0) = bits 19 – 16 (MSB)
Internal/External
frequency reference 0 = internal. Use the internal 60
MHz clock (from the USB PHY)
as frequency reference.
1 = external. Use the 10 MHz
clock externally supplied
through J7 as frequency
reference.
REG2(7)
Symbol rate
f
symbol rate tx
The modulator symbol rate is in
the form
f
symbol rate tx
= f
clk_tx
/ 2
n
where n ranges from 0 (1 sample
per symbol) to 15 (symbol rate =
f
clk_tx
/ 32768).
n is defined in REG3(3:0)
Modulation Index
h
Modulation index h. Format 3.8
Thus, 0x0080 represents an index of
0.5. (MSK).
Valid range: 0 – 7.996
REG4(7:0): LSB, after decimal point
REG6(7:5): MSB, before decimal
point
Modulation type 0 = 2-FSK
1 = 2-GFSK
2 = 4-FSK
3 = 4-GMSK
4 = 8-FSK
5 = 8-GMSK
REG5(5:0)
Continuous vs
burst modulation 0 = burst mode
1 = continuous mode
While in continuous mode, the
following configuration parameters
are ignored: packet size, window
start and stop times.
REG5(6)
Gaussian Filter
BT 0 = BT 0.3
1 = BT 0.5
REG5(7)
Output Center
frequency (
f
c_tx
)
Frequency translation.
32-bit signed integer (2’s
complement representation)
expressed as
f
c_tx
* 2
32
/
f
clk_tx
For a clean output waveform, we
recommend keeping the maximum
frequency (center fre ½
symbol rate) below 1/10
th
of the
processing clock f
clk_tx
.
REG57: LSB
REG58
REG59
REG60: MSB
Input selection /
format, test
modes Select the origin of the modulator
input data stream.
0 = high-speed USB, 8-bit parallel
1 = LAN/TCP-IP, port 1024
(through Ethernet adapter), 8-bit
parallel
2 = from left J6 connector (Many
comblocks), 1-bit serial
3 = internal generation of 2047-bit
periodic pseudo-random bit sequence
(with BCH encoding when enabled)
4 = internal generation of modulo-
256 counting test sequence. (with
BCH encoding only)