GRMON3-UM
June 2019, Version 3.1.0
35
www.cobham.com/gaisler
grmon> ei stat en
Error injection statistics enabled
grmon> run
...
grmon> ei stat
itag : 5/ 5 (100.0%) idata: 5/ 18 ( 27.8%)
dtag : 1/ 1 (100.0%) ddata: 4/ 22 ( 18.2%)
IU RF : 4/ 10 ( 25.0%)
FPU RF: 0/ 4 ( 0.0%)
Total : 19/ 60 ( 31.7%)
grmon>
NOTE: The real time elapsed is always greater than LEON CPU experienced since the LEON is stopped during
error injection. Times and rates given to GRMON are relative the experienced time of the LEON. The time the
LEON is stopped is taken into account by GRMON, however minor differences is to be expected.
3.11. FLASH programming
3.11.1. CFI compatible Flash PROM
GRMON supports programming of CFI compatible flash PROMs attached to the external memory bus, through the
flash command. Flash programming is only supported if the target system contains one of the following memory
controllers MCTRL, FTMCTRL, FTSRCTRL or SSRCTRL. The PROM bus width can be 8-, 16- or 32-bit. It is
imperative that the PROM width in the MCFG1 register correctly reflects the width of the external PROM.
To program 8-bit and 16-bit PROMs, GRMON must be able to do byte (or half-word) accesses to the target system.
To support this either connect with a JTAG debug link or have at least one working SRAM/SDRAM bank and
a CPU available in the target system.
Programming the EDAC checkbits for 8- or 32-bit PROMs is also supported. GRMON will automatically program
the checkbits if EDAC is enabled. EDAC can be enabled by the
commandline option, using the mcfg3
command or setting the register bit via the TCL variable
. When programming 32-bit
EDAC checkbits it is required that no other AHB master is accessing the memory. Other masters can for example
be DMA or Spacewire RMAP accesses. When programming 8-bit EDAC checkbits, GRMON will ignore any data
that should have been written to the EDAC area of the memory.
There are many different suppliers of CFI devices, and some implements their own command set. The command
set is specified by the CFI query register 14 (MSB) and 13 (LSB). The value for these register can in most cases
be found in the datasheet of the CFI device. GRMON supports the command sets that are listed in Table 3.4,
“Supported CFI command set”.
Table 3.4. Supported CFI command set
Q13
Q14
Description
0x01 0x00 Intel/Sharp Extended Command Set
0x02 0x00 AMD/Fujitsu Standard Command Set
0x03 0x00 Intel Standard Command Set
0x00 0x02 Intel Performance Code Command
Some flash chips provides lock protection to prevent the flash from being accidentally written. The user is required
to actively lock and unlock the flash. Note that the memory controller can disable all write cycles to the flash also,
however GRMON automatically enables PROM write access before the flash is accessed.
The flash device configuration is auto-detected, the information is printed out like in the example below. One can
verify the configuration so that the auto-detection is correct if problems are experienced. The block lock status (if
implement by the flash chip) can be viewed like in the following example:
grmon3> flash
Manuf. : Intel
Device : MT28F640J3
