GR740-UM-DS, Nov 2017, Version 1.7
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GR740
18.2.6 Transaction ordering
The bridge implements first-come, first-served ordering and will keep track of the order of incoming
accesses. The accesses will then be served in the same order. For instance, if master 0 initiates an
access to the bridge, followed by master 3 and then master 5, the bridge will propagate the access
from master 0 (and respond with SPLIT on a read access) and then respond with SPLIT to the other
masters. When the bridge has a response for master 0, this master will be allowed in arbitration again
by the bridge asserting HSPLIT. When the bridge has finished serving master 0 it will allow the next
queued master in arbitration, in this case master 3. Other incoming masters will receive SPLIT
responses and will not be allowed in arbitration until all previous masters have been served.
An incoming locked access will always be given precedence over any other masters in the queue.
18.2.7 Core latency
The delay incurred when performing an access over the core depends on several parameters such as
the operating frequency of the AMBA buses and memory access patterns. Table 362 below shows one
example of core behavior.
Read burst to prefetchable area -
Burst of 32-bit accesses up to 32-byte address boundary.
Read burst to non-prefetchable
area
Access size <=
32-bits
Incremental read burst of same access size as on slave interface, the
length is the same as the length of the incoming burst. The master
interface will insert BUSY cycles between the sequential accesses.
Read burst to non-prefetchable
area
Access size >
32-bits
Burst of 32-bit accesses. Length of burst:
(incoming burst length)*(access size)/(32 bits)
Single write
Access size <=
32-bits
Single write access of same size
Single write
Access size >
32-bits
Burst of 32-bit accesses. Length of burst: (access size)/(32 bits).
Write burst
-
Burst of 32-bit accesses
Table 362.
Example of single read
Clock cycle
Core slave side activity
Core master side activity
0
Discovers access and transitions from idle state
Idle
1
Slave side waits for master side, SPLIT response
is given to incoming access, any new incoming
accesses also receive SPLIT responses.
Discovers slave side transition. Master interface output
signals are assigned.
2
If bus access is granted, perform address phase. Other-
wise wait for bus grant.
3
Register read data and transition to data ready state.
4
Discovers that read data is ready, assign read
data output and assign SPLIT complete
Idle
5
SPLIT complete output is HIGH
6
Typically a wait cycle for the SPLIT:ed master to
be allowed into arbitration. Core waits for master
to return. Other masters receive SPLIT
responses.
7
Master has been allowed into arbitration and per-
forms address phase. Core keeps HREADY high
8
Access data phase. Core has returned to idle
state.
Table 361.
Read and write combining
Access on slave interface
Access size
Resulting access(es) on master interface
