BAT32G1x9 user manual | Chapter 10 Timer M
344 / 1149
Rev.1.02
10.3.15
Timer M status register 1 (TMSR1).
Figure 10-26 Format of timer M status register 1 (TMSR1) [Input Capture Function].
Address: 0x40042A83
reset:
00H R/W
symbol
TMSR1
UDF
Underflow flag
Not valid when using the input capture feature.
OVF
Overflow flag
note
1
[condition for
"0"].
After reading write "0"
Note
2
.
[condition for
"1"].
When an overflow occurs in
TM1
IMFD
Enter the capture/compare match flag
D
Note
5
[condition for
"0"].
After reading write "0"
Note
2
.
[condition for
"1"].
Note
3
on the input edge of the TMIOD1 pin
IMFC
Enter the capture/compare match flag
C
Note
5
[condition for
"0"].
After reading write "0"
Note
2
.
[condition for
"1"].
The input edge of the
TMIOC1 pin
is note
3
IMFB
Enter the capture/compare match flag
B
Note
5
[condition for
"0"].
After reading write "0"
Note
2
.
[condition for
"1"].
The input edge of the TMIOB1 pin
is note
4
IMFA
Enter the capture/compare match flag
A
note
5
[condition for
"0"].
After reading write "0"
Note
2
.
[condition for
"1"].
The input edge of the
TMIOA1 pin
is note
4
Note 1
When the
count value of
timerM1
changes from
"FFFFH"
to
"0000H", the overflow flag changes to
"1". In
addition, according to the
setting of
the CCLR0~CCLR2
bit
of
the TMCR1
register, if the
count value of
timer
M1 is changed
from
" FFFFH"
becomes "0000H"
and the overflow sign becomes "1".
7
6
5
4
3
2 1
0
0
0
UDF
OVF
IMFD
IMFC
IMFB
IMFA