CMT2380F17
Rev0.1 | 204/347
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18.4
Frame Error Detection
When used for framing error detection, the UART0 looks for missing stop bits in the communication. A
missing stop bit will set the FE bit in the S0CON register. The FE bit shares the S0CON.7 bit with SM00 and
the function of S0CON.7 is determined by SMOD0 bit (PCON.6). If SMOD0 is set then S0CON.7 functions as
FE. S0CON.7 functions as SM00 when SMOD0 is cleared. When S0CON.7 functions as FE, it can only be
cleared by firmware. Refer to Figure 18
–7.
D1
D2
D3
D4
D5
D6
Start
D0
Stop
D8
D7
9-bit data
SET FE bit if STOP=0
SM00 to UART mode control
PCON0.SMOD0
S0CON
RI0
TI0
RB80
TB80
REN0
SM20
SM10
SM00/
FE
Figure 18-7. UART0 Frame Error Detection
18.5
Multiprocessor Communications
Modes 2 and 3 have a special provision for multiprocessor communications as shown in Figure 18
–8. In
these two modes, 9 data bits are received. The 9th bit goes into RB80. Then comes a stop bit. The port can
be programmed such that when the stop bit is received, the serial port interrupt will be activated only if
RB80=1. This feature is enabled by setting bit SM20 (in S0CON register). A way to use this feature in
multiprocessor systems is as follows:
When the master processor wants to transmit a block of data to one of several slaves, it first sends out an
address byte which identifies the target slave. An address byte differs from a data byte in that the 9th bit is 1 in
an address byte and 0 in a data byte. With SM20=1, no slave will be interrupted by a data byte. An address
byte, however, will interrupt all slaves, so that each slave can examine the received byte and check if it is
being addressed. The addressed slave will clear its SM20 bit and prepare to receive the data bytes that will be
coming. The slaves that weren’t being addressed leave their SM20 set and go on about their business,
ignoring the coming data bytes.
SM20 has no effect in Mode 0, and in Mode 1 can be used to check the validity of the stop bit. In a Mode
1 reception, if SM20=1, the receive interrupt will not be activated unless a valid stop bit is received.
Slave 3
Slave 2
Slave 1
Master
R
VCC
Pull-up
TX
RX
RX
RX
RX
TX
TX
TX
Figure 18-8. UART0 Multiprocessor Communications
18.6
Automatic Address Recognition
Summary of Contents for CMT2380F17
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Page 177: ...CMT2380F17 Rev0 1 177 347 www cmostek com Figure 17 3 PCA Interrupt System...
Page 246: ...CMT2380F17 Rev0 1 246 347 www cmostek com SnMIPS S0MI S1MI 1 P3 3 P4 7...