Clevo NP50DB, Service Manual

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Schematic Diagrams
PCH 9/9 B - 33
B.Schematic Diagrams
PCH 9/9
Sheet 32 of 59
PCH 9/9
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
NO REBOOThis signal has an integrated weak
pull-down resistor (20 KΩ nominal) to
disable the no reboot strap functionality
by default.
To enable no reboot on TCO Timer
expiration, this signal should be
pulled-up to V3.3S through a 1k to 2.2 KΩ
± 5% resistor.
BOOT STARP
This signal has an integrated weak
pull-down resistor (20 KΩ nominal)
to default boot from SPI.
To enable boot to LPC, this signal
should be pulled up to V3.3S through
a 1k to 2.2 KΩ ± 5% resistor.
嶇
BIOS
䡢 娵
嶇
BIOS
䡢 娵
嶇
BIOS
䡢 娵
GPIO
H: W / TPM
L: W/O TPM
Differential between RCOMPN/RCOMPP.
Length matched to less than 1% trace.
XTAL SELECT-1
HIGH -> 24 MHZ
LOW -> 38.4 MHZ
M.2 CNVI STRAP
HIGH -> DISABLE
LOW -> ENABLE
Leakage
DEBUG BOT
TX -> D+
RX -> D-
Close to M.2
Close to M.2
Rubband
2019/12/23
ID1
ID2
G61 G62
Psys=6.04K
High
High
Low
Low
ID1
ID2
G61 G62
Psys=19.6K
Low
High
High
Low
120W
150W
ID1
ID2
LPSS_GSPI0_MOSI
LPSS_GSPI1_MOSI
PCH_2_CPU_TRIGGER_R
BOARD_ID2
LPSS_GSPI1_MOSI
TPM_DET
TPM_DET
SB_BLON
PCIECOMP_N
PCIECOMP_P
CNV_W T_RCOMP
SD3_RCOMP_1P8
SD3_RCOMP_3P3
GPPJ_RCOMP_1P8
CNVI_BRI_DT
CNVI_RGI_DT
GPP_J1
SMI#_R
SMI#_R
LPSS_GSPI0_MOSI
UART2_RXD
UART2_TXD
SB_BLON
DGPU_PW M_SELECT#
3G_CONFIG2
BOARD_ID1
3.3VS
3.3VA
3.3VS
3.3VS
3.3VS
VDD3
PCH1.8VA
PCH1.8VA
PCH1.8VA
3.3VS
PCH1.8VA PCH1.8VA
CPU_2_PCH_TRIGGER 6
PCH_2_CPU_TRIGGER 6
CNVI_MFUART2_RXD 34
CNVI_GNSS_PA_BLANKING 34
CNVI_W GR_CLKP 34
CNVI_W GR_CLKN 34
CNVI_W GR_D0N 34
CNVI_W GR_D0P 34
CNVI_W GR_D1N 34
CNVI_W GR_D1P 34
CNVI_W T_CLKN 34
CNVI_W T_CLKP 34
CNVI_W T_D0N 34
CNVI_W T_D0P 34
CNVI_W T_D1N 34
CNVI_W T_D1P 34
CNVI_BRI_DT 34
CNVI_RGI_DT 34
CNVI_MFUART2_TXD 34
H_SKTOCC_N 4,28
GPP_J1 42,47
H_TRST# 4
H_PREQ# 4
H_PRDY# 4
GPIO4_1V8_MAIN_EN_R 18
CNVI_BRI_RSP 34
CNVI_RGI_RSP 34
CNVI_DET# 34,39
I2C_SCL_TP 37
I2C_SDA_TP 37 SB_BLON 22
SATA_PW R_EN 37
VDD3 4,24,25,27,30,33,34,36,38,39,40,41,42,43,46,47,49,50,51,52,53,54,55
3.3VA 4,24,25,26,27,30,38,42,47
PCH1.8VA 30
3.3VS 8,9,16,17,18,21,22,23,24,25,26,27,28,29,33,34,36,37,38,39,41,42,44,46
SMI# 24,28,39
Title
Size Document Number R e v
Date: Sheet o f
6-71-NP500-D02
D02
[32] PCH 10_11/12-UART/I2C/GPIO
A3
32 59 Monday, February 24, 2020
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
N18P
Title
Size Document Number R e v
Date: Sheet o f
6-71-NP500-D02
D02
[32] PCH 10_11/12-UART/I2C/GPIO
A3
32 59 Monday, February 24, 2020
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
N18P
Title
Size Document Number R e v
Date: Sheet o f
6-71-NP500-D02
D02
[32] PCH 10_11/12-UART/I2C/GPIO
A3
32 59 Monday, February 24, 2020
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
N18P
R132
100K_04
W /O TPM
R468 200_1%_04
PCH
R494 *0_06 PCH
13 OF 13
?
?
?
?
U27M
CML-H QS64
PCH
CNV_WR_CLKN
BD4
CNV_WR_CLKP
BE3
CNV_WR_D0N
BB3
CNV_WR_D0P
BB4
CNV_WR_D1N
BA3
CNV_WR_D1P
BA2
CNV_WT_CLKN
BC5
CNV_WT_CLKP
BB6
CNV_WT_D0N
BE6
CNV_WT_D0P
BD7
CNV_WT_D1N
BG6
CNV_WT_D1P
BF6
CNV_WT_RCOMP
BA1
GPPJ_RCOMP_1P81
BD1
GPPJ_RCOMP_1P82
BE1
GPP_J0/CNV_PA_BLANKING
AV6
GPP_I11/M2_SKT2_CFG0
AP3
GPP_G7/SD_WP
AV13
GPP_G5/SD_CD#
BE8
GPP_I12/M2_SKT2_CFG1
AP2
PCIE_RCOMPN
B12
GPP_J9/CNV_MFUART2_TXD
AU9
GPP_I13/M2_SKT2_CFG2
AN4
GPP_I14/M2_SKT2_CFG3
AM7
PCIE_RCOMPP
A13
GPP_G6/SD_CLK
BD8
GPP_J8/CNV_MFUART2_RXD
AW2
GPP_J10
AV7
TP
AL35
RSVD2
Y35
GPP_J11/A4WP_PRESENT
AR13
RSVD1
BC1
GPP_J2
AW3
GPP_G4/SD_DATA3
BG8
GPP_J3
AT10
GPP_J7/CNV_RGI_RSP/UART0B_CTS#
AV3
GPP_J1/CPU_C10_GATE#
AY3
GPP_J4/CNV_BRI_DT/UART0B_RTS#
AV4
SD_1P8_RCOMP
BE5
GPP_J5/CNV_BRI_RSP/UART0B_RXD
AY2
GPP_J6/CNV_RGI_DT/UART0B_TXD
BA4
SD_3P3_RCOMP
BE4
GPP_G3/SD_DATA2
BF9
GPPJ_RCOMP_1P83
BE2
GPP_G2/SD_DATA1
BF8
RSVD3
Y36
GPP_G0/SD_CMD
AW13
GPP_G1/SD_DATA0
BE9
R153
*4.7K_04 PCH
PCH
T24
PCH
10 OF 13
?
?
?
?
U27J
CML-H QS64
PCH
TRIGGER_OUT
AK3
TRIGGER_IN
AK2
CPU_TRST#
AM4
PREQ#
AL2
RSVD4
R32
RSVD3
N32
PRDY#
AM5
RSVD2
AH15
RSVD1
AH14
RSVD8
Y15
RSVD7
Y14
RSVD6
U37
RSVD5
U35
R456 150_1%_04 PCH
R110 200_1%_04
PCH
R119
*10K_04
PCH
R458 100K_04
PCH
R121
4.7K_04
PCH
R445
*20K_04
PCH
R470 10K_04
PCH
T22
PCH
R129 *100K_04 NP50 ID
R476 100K_04 G61 ID
R449 30.1_1%_04
PCH
R457
10K_04
PCH
R454 200_1%_04
PCH
R116 100K_04
PCH
R127
20K_04
PCH
R453
*20K_04
PCH
T20
PCH
R447 22_04
PCH
R156 *0_04
PCH
11 OF 13
?
?
?
?
U27K
CML-H QS64
PCH
GPP_C22/UART2_RTS#
AW21
GPP_C20/UART2_RXD
BD20
GPP_D13/ISH_UART0_RXD/I2C2_SDA
BE17
GPP_C23/UART2_CTS#
AV21
GPP_D12/ISH_SPI_MOSI/GP_BSSB_DI/GSPI2_MOSI
AN18
GPP_C18/I2C1_SDA
BF21
GPP_C19/I2C1_SCL
BE21
GPP_C13/UART1_TXD/ISH_UART1_TXD
AP21
GPP_D14/ISH_UART0_TXD/I2C2_SCL
BF17
GPP_H20/ISH_I2C0_SCL
AG45
GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7
BD38
GPP_C12/UART1_RXD/ISH_UART1_RXD
AU24
GPP_B16/GSPI0_CLK
BF29
GPP_D16/ISH_UART0_CTS#/CNV_WCEN
BF14
GPP_B15/GSPI0_CS0#
BB26
GPP_A23/ISH_GP5
AV34
GPP_D10/ISH_SPI_CLK/GSPI2_CLK
BB20
GPP_H22/ISH_I2C1_SCL
AH47
GPP_A22/ISH_GP4
AW32
GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#/CNV_WFEN
AR18
GPP_H19/ISH_I2C0_SDA
AH46
GPP_C17/I2C0_SCL
BC22
GPP_C16/I2C0_SDA
BF23
GPP_D23/ISH_I2C2_SCL/I2C3_SCL
BE14
GPP_A19/ISH_GP1
BD34
GPP_D11/ISH_SPI_MISO/GP_BSSB_CLK/GSPI2_MISO
BB16
GPP_A21/ISH_GP3
BA33
GPP_D9/ISH_SPI_CS#/GSPI2_CS0#
BA20
GPP_H21/ISH_I2C1_SDA
AH48
GPP_C21/UART2_TXD
BE20
GPP_C15/UART1_CTS#/ISH_UART1_CTS#
BD21
GPP_A18/ISH_GP0
BF35
GPP_A20/ISH_GP2
BE34
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
AW24
GPP_C11/UART0A_CTS#
AP24
GPP_C8/UART0A_RXD
BE23
GPP_D4/ISH_I2C2_SDA/I2C3_SDA/SBK4/BK4
BE15
GPP_C10/UART0A_RTS#
BA24
GPP_C9/UART0A_TXD
BB24
GPP_B21/GSPI1_MISO
BD30
GPP_B22/GSPI1_MOSI
BA26
GPP_B17/GSPI0_MISO
BD29
GPP_B19/GSPI1_CS0#
AW26
GPP_B18/GSPI0_MOSI
BE30
GPP_B20/GSPI1_CLK
AU26
R477 100K_04 G62 ID
R131
10K_04
W / TPM
R126 75K_04
PCH
R455 22_04
PCH
R690 0_04
PCH
R174 *10K_04
PCH
R111 10K_04
PCH
PCH
R130 100K_04 NP50 ID
R492 *0_06
PCH
R490 100_1%_04 PCH
R176
*4.7K_04 PCH