Clear-Com 4000 series II, Technical Manual

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4000 Digital Series
II
Issue 2.1 Technical Manual
STA0381 Page 65
U3 pr12V for the analogue electronics and TR1/U4/U29 provide a -7.5V rail.
U17 is the 68000 control CPU, which runs bootstrap code, fitted at U18 and non-volatile downloaded
code from the matrix stored in U22.
U19 is a 1Mbit static ram for all volatile data.
U25 is a dual channel UART, one channel for serial communication with the matrix and the other a
spare.
U26 is an FPGA, the function of which is programmable and stored as part of the bootstrap Prom.
This board provides all necessary decode logic for the following connectors:
CON10 is an extension panel interface, which also allows for connection of the PDE3530 I2C card.
CON7 is for a display interface.
CON8 is for the GPI interface.
CON13 is for an RJ45 interface to the matrix.
CON11 is the PDE4536 interface.
CON16 is the spare RS232 interface.
CON17 is for PDE3561 serial interface (NB U28 must be removed if this is used)
3.11 PDE 4551 Key/LCD Display Card
Figure 59 - PDE4551 Key/LCD Display Card
This card contains the 40 keys and associated LEDs for the PD4224 key display panel.
The keys and LEDs are arranged in a matrix of rows and columns to reduce interconnection.
U18-22 perform the decode circuitry necessary to drive these signals.
A buck mode switching regulator ,U1,is used to generate 5Volts for the electronics and switches and
displays.
U16 provides DTMF tones decoded from U14 when the main panel processor card writes to LED
positions.
VR2 is a preset for adjusting the amount of DTMF to the loudspeaker also controlled by the AUX
encoder on the front panel.
DTMF tones sent to the matrix are fixed in level.
The LCD displays are driven by industry standard 80 column LCD driver and LCD controller ics.
VR1 is a preset allowing for viewing angle adjustment of the displays.